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The programmable logic-in-memory (PLiM) computer

Published: 14 March 2016 Publication History

Abstract

Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits with a limited performance overhead as compared to the standard computation paradigms. This paper takes a major step along this direction by proposing a fully-programmable in-memory computing system. In particular, we address, for the first time, the question of controlling the in-memory computation, by proposing a lightweight unit managing the operations performed on a memristive array. Assembly-level programming abstraction is achieved by a natively-implemented majority and complement operator. This platform enables diverse sets of applications to be ported with little effort. As a case study, we present a standardized symmetric-key cipher for lightweight security applications. The detailed system design flow and simulation results with accurate device models are reported validating the approach.

References

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G. W. Burr et al., "Overview of candidate device technologies for storage-class-memory," IBM J. R&D, 52(4/5), 2008.
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T. You et al., "Exploiting Memristive BiFeO3 Bilayer Structures for Compact Sequential Logics," Adv. Func. Mat., 24(3357), 2014.
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Cited By

View all
  • (2022)Parallel Computing of Graph-based Functions in ReRAMACM Journal on Emerging Technologies in Computing Systems10.1145/345316318:2(1-24)Online publication date: 12-Jan-2022
  • (2019)Memristors for Programmable Circuits Controlled by Embedded SystemsProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323985(37-40)Online publication date: 27-May-2019
  • (2019)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add OperationsACM Transactions on Design Automation of Electronic Systems10.1145/330649524:2(1-22)Online publication date: 21-Mar-2019
  • Show More Cited By

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Information & Contributors

Information

Published In

cover image Guide Proceedings
DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
March 2016
1779 pages
ISBN:9783981537062
  • General Chair:
  • Luca Fanucci,
  • Program Chair:
  • Jürgen Teich

Sponsors

  • IMEC: IMEC
  • Systematic: Systematic Paris-Region Systems & ICT Cluster
  • DREWAG: DREWAG
  • AENEAS: AENEAS
  • Technical University of Dresden
  • CMP: Circuits Multi Projets
  • PENTA: PENTA
  • CISCO
  • OFFIS: Oldenburger Institut für Informatik
  • Goethe University: Goethe University Frankfurt

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 14 March 2016

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Cited By

View all
  • (2022)Parallel Computing of Graph-based Functions in ReRAMACM Journal on Emerging Technologies in Computing Systems10.1145/345316318:2(1-24)Online publication date: 12-Jan-2022
  • (2019)Memristors for Programmable Circuits Controlled by Embedded SystemsProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323985(37-40)Online publication date: 27-May-2019
  • (2019)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add OperationsACM Transactions on Design Automation of Electronic Systems10.1145/330649524:2(1-22)Online publication date: 21-Mar-2019
  • (2019)A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based CrossbarProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317972(195-200)Online publication date: 13-May-2019
  • (2018)Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar ArraysACM Journal on Emerging Technologies in Computing Systems10.1145/318335214:2(1-14)Online publication date: 12-Jul-2018
  • (2017)Endurance management for resistive logic-in-memory computing architecturesProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130638(1092-1097)Online publication date: 27-Mar-2017
  • (2017)ReVAMPProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130568(782-787)Online publication date: 27-Mar-2017
  • (2016)Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972026(948-953)Online publication date: 14-Mar-2016

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