research-article

SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware

Authors:

Shervin Roshanisefat,

Hadi Mardani Kamali,

Avesta SasanAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 153 - 158

https://doi.org/10.1145/3194554.3194596

Published: 30 May 2018 Publication History

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Abstract

In this paper, we claim that cyclic obfuscation, when properly implemented, poses exponential complexity on SAT or CycSAT attack. The CycSAT, in order to generate the necessary cycle avoidance clauses, uses a pre-processing step. We show that this pre-processing step has to compose its cycle avoidance condition on all cycles in a netlist, otherwise, a missing cycle could trap the SAT solver in an infinite loop or force it to return an incorrect key. Then, we propose several techniques by which the number of cycles is exponentially increased with respect to the number of inserted feedbacks. We further illustrate that when the number of feedbacks is increased, the pre-processing step of CycSAT faces an exponential increase in complexity and runtime, preventing the correct composition of loop avoidance clauses in a reasonable time before invoking the SAT solver. On the other hand, if the pre-processing is not completed properly, the SAT solver will get stuck or return incorrect key. Hence, when the cyclic obfuscation in accordance to the conditions proposed in this paper is implemented, it would impose an exponential complexity with respect to the number of inserted feedback, even when the CycSAT solution is used.

References

[1]

V. Agarwal, N. Kankani, R. Rao, S. Bhardwaj, and J. Wang. 2005. An efficient combinationality check technique for the synthesis of cyclic combinational circuits Proc. of the ASP-DAC. 212--215. S. Ray, and S. Malik. 2015. Evaluating the security of logic encryption algorithms 2015 IEEE Int. Symp. on Hardware Oriented Security and Trust (HOST). 137--143.

Digital Library

Google Scholar

[2]

Y. Xie and A. Srivastava. 2016. Mitigating sat attack on logic locking. In International Conference on Cryptographic Hardware and Embedded Systems. Springer, 127--146.

Google Scholar

[3]

M. Yasin, B. Mazumdar, J. J. V. Rajendran, and O. Sinanoglu. 2016. SARLock: SAT attack resistant logic locking. In 2016 IEEE Int. Symp. on Hardware Oriented Security and Trust (HOST). 236--241.

Google Scholar

[4]

M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. 2017. Security analysis of Anti-SAT. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). 342--347.

Google Scholar

[5]

J. Zhang. 2016. A Practical Logic Obfuscation Technique for Hardware Security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, 3 (March. 2016), 1193--1197. ISSN1063-8210

Digital Library

Google Scholar

[6]

H. Zhou, R. Jiang, and S. Kong. 2017. CycSAT: SAT-based attack on cyclic logic encryptions 2017 IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD). 49--56.

Digital Library

Google Scholar

Cited By

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Chen XZheng DHuang K(2024)FCLock: harnessing functional non-combinational cycles in logic lockingIEICE Electronics Express10.1587/elex.21.2024021821:12(20240218-20240218)Online publication date: 25-Jun-2024
https://doi.org/10.1587/elex.21.20240218
McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Wang JChen ZZhang JXu YYu TZheng ZYe EGeorge SYang HLiu YNi KNarayanan VLi X(2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3640462
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Index Terms

SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware
1. Security and privacy
  1. Security in hardware

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Information & Contributors

Information

Published In

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2018

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GLSVLSI '18

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SIGDA

GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

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GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all

Chen XZheng DHuang K(2024)FCLock: harnessing functional non-combinational cycles in logic lockingIEICE Electronics Express10.1587/elex.21.2024021821:12(20240218-20240218)Online publication date: 25-Jun-2024
https://doi.org/10.1587/elex.21.20240218
McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Wang JChen ZZhang JXu YYu TZheng ZYe EGeorge SYang HLiu YNi KNarayanan VLi X(2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3640462
Azar KKamali HFarahmandi FTehranipoor M(2024)Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335728619(2771-2785)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TIFS.2024.3357286
Chen PYang XHe YChen YLi YWang CKim T(2024)LOOPLock 3.0: A Robust Cyclic Logic Locking ApproachProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473877(594-599)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473877
Subbiah KChinnathevar S(2024)A Survey on Logic-Locking Characteristics and AttacksJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01017-y105:4(1073-1087)Online publication date: 7-Mar-2024
https://doi.org/10.1007/s40031-024-01017-y
Kalyani A(2024)Hardware Security for IC Piracy: Logic Locking Past, Present and OpportunityAdvances in Microelectronics, Embedded Systems and IoT10.1007/978-981-97-0767-6_1(1-11)Online publication date: 19-May-2024
https://doi.org/10.1007/978-981-97-0767-6_1
Tehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi F(2024)Advances in Logic LockingHardware Security10.1007/978-3-031-58687-3_2(53-142)Online publication date: 3-Apr-2024
https://doi.org/10.1007/978-3-031-58687-3_2
Muttaki MSaha SKamali HRahman FTehranipoor MFarahmandi F(2023)RTLock: IP Protection using Scan-Aware Logic Locking at RTL2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137136(1-6)Online publication date: Apr-2023
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Ziyang YIkeda M(2023)Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321882(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321882
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Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

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