research-article

Ending Piracy of Integrated Circuits

Authors:

Jarrod A. Roy,

Farinaz Koushanfar,

Igor L. MarkovAuthors Info & Claims

Computer, Volume 43, Issue 10

Pages 30 - 38

https://doi.org/10.1109/MC.2010.284

Published: 01 October 2010 Publication History

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Abstract

An effective technique to combat IC piracy is to render infringement impractical by making physical tampering unprofitable and attacks computationally infeasible. EPIC accomplishes this using a novel low-overhead combinational chip-locking system and a chip-activation protocol based on public-key cryptography.

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Rathor VSingh MSahoo KMohanty S(2024)GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic LockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.334035032:2(361-371)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3340350
Azar KKamali HFarahmandi FTehranipoor M(2024)Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335728619(2771-2785)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TIFS.2024.3357286
Chen PYang XHe YChen YLi YWang CKim T(2024)LOOPLock 3.0: A Robust Cyclic Logic Locking ApproachProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473877(594-599)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473877
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Published In

Computer Volume 43, Issue 10

October 2010

83 pages

ISSN:0018-9162

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 October 2010

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Rathor VSingh MSahoo KMohanty S(2024)GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic LockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.334035032:2(361-371)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3340350
Azar KKamali HFarahmandi FTehranipoor M(2024)Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An ExplorationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.335728619(2771-2785)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TIFS.2024.3357286
Chen PYang XHe YChen YLi YWang CKim T(2024)LOOPLock 3.0: A Robust Cyclic Logic Locking ApproachProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473877(594-599)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473877
Mittu PLiu YSrivastava AThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)TimingCamouflage+ DecamouflagedProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590238(575-580)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590238
Díaz-Rizo AAboushady HStratigopoulos H(2023)Leaking Wireless ICs via Hardware Trojan-Infected SynchronizationIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.321850720:5(3845-3859)Online publication date: 31-Aug-2023
https://dl.acm.org/doi/10.1109/TDSC.2022.3218507
Hu YZhang YYang KChen DBeerel PNuzzo P(2023)On the Security of Sequential Logic Locking Against Oracle-Guided AttacksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325342842:11(3628-3641)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3253428
Muttaki MMohammadivojdan RKamali HTehranipoor MFarahmandi F(2023)HLock+: A Robust and Low-Overhead Logic Locking at the High-Level LanguageIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321579642:7(2149-2162)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3215796
Li LOrailoglu A(2023)Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319279342:4(1044-1057)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3192793
Naveenkumar RSivamangai NNapolean APriya SAshika S(2023)Design of INV/BUFF Logic Locking For Enhancing the Hardware SecurityJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06061-y39:2(141-153)Online publication date: 5-May-2023
https://dl.acm.org/doi/10.1007/s10836-023-06061-y
Aljafar MAzaïs FFlottes MPagliarini SChang CRührmair UMukhopadhyay DForte D(2022)Leveraging Layout-based Effects for Locking Analog ICsProceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security10.1145/3560834.3563826(5-13)Online publication date: 11-Nov-2022
https://dl.acm.org/doi/10.1145/3560834.3563826
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Managing Digital Piracy: Pricing and Protection

Examining Digital Piracy: Self-Control, Punishment, and Self-Efficacy

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