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A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems

Authors:

Amin Jadidi,

Mohammad Arjomand,

Mahmut Kandemir,

Chita DasAuthors Info & Claims

ACM SIGMETRICS Performance Evaluation Review, Volume 45, Issue 1

Pages 27 - 28

https://doi.org/10.1145/3143314.3078547

Published: 05 June 2017 Publication History

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Abstract

This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM).Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly,while the other half are write-friendly--this asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC)mode.Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache(L3) access energy for various workloads.

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[1]

Amin Jadidi, Mohammad Arjomand, Mahmut T. Kandemir, and Chita R. Das. A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems, 2017. http://arxiv.org/abs/1704.05044

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Jadidi AKandemir MDas C(2020)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00051(290-298)Online publication date: Mar-2020
https://doi.org/10.1109/PDP50117.2020.00051
Qureshi MKim HKim S(2019)A Restore-Free Mode for MLC STT-RAM CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289989427:6(1465-1469)Online publication date: 20-May-2019
https://dl.acm.org/doi/10.1109/TVLSI.2019.2899894
Donvanavard BMonazzah ADutt NMuck T(2018)Exploring Hybrid Memory Caches in Chip Multiprocessors2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449386(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449386
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Index Terms

A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory

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Information & Contributors

Information

Published In

ACM SIGMETRICS Performance Evaluation Review Volume 45, Issue 1

Performance evaluation review

June 2017

70 pages

ISSN:0163-5999

DOI:10.1145/3143314

Editor:
Nidhi Hegde
Bell Labs, Nokia

Issue’s Table of Contents

SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems
June 2017
84 pages
ISBN:9781450350327
DOI:10.1145/3078505
General Chairs:
Bruce Hajek
University of Illinois
,
Sewoong Oh
University of Illinois
,
Program Chairs:
Augustin Chaintreau
Columbia University
,
Leana Golubchik
University of Southern California
,
Zhi-Li Zhang
University of Minnesota

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2017

Published in SIGMETRICS Volume 45, Issue 1

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Cited By

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Jadidi AKandemir MDas C(2020)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00051(290-298)Online publication date: Mar-2020
https://doi.org/10.1109/PDP50117.2020.00051
Qureshi MKim HKim S(2019)A Restore-Free Mode for MLC STT-RAM CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289989427:6(1465-1469)Online publication date: 20-May-2019
https://dl.acm.org/doi/10.1109/TVLSI.2019.2899894
Donvanavard BMonazzah ADutt NMuck T(2018)Exploring Hybrid Memory Caches in Chip Multiprocessors2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449386(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449386
Ramezani MElyasi NArjomand MKandemir MSivasubramaniam A(2017)Exploring the impact of memory block permutation on performance of a crossbar ReRAM main memory2017 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2017.8167774(167-176)Online publication date: Oct-2017
https://doi.org/10.1109/IISWC.2017.8167774
Arjomand MJadidi AKandemir MDas C(2017)Leveraging value locality for efficient design of a hybrid cache in multicore processors2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203753(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203753
Jadidi AArjomand MKandemir MDas C(2018)Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPsIEEE Transactions on Computers10.1109/TC.2018.279606767:7(1054-1061)Online publication date: 1-Jul-2018
https://doi.org/10.1109/TC.2018.2796067
Arjomand MJadidi AKandemir MDas CParameswaran S(2017)Leveraging value locality for efficient design of a hybrid cache in multicore processorsProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199701(1-8)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199701
Jadidi AArjomand MKandemir MDas C(2017)A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core SystemsACM SIGMETRICS Performance Evaluation Review10.1145/3143314.307854745:1(27-28)Online publication date: 5-Jun-2017
https://dl.acm.org/doi/10.1145/3143314.3078547
Jadidi AArjomand MKandemir MDas CHajek BOh SChaintreau AGolubchik LZhang Z(2017)A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core SystemsProceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems10.1145/3078505.3078547(27-28)Online publication date: 5-Jun-2017
https://dl.acm.org/doi/10.1145/3078505.3078547

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