research-article

A Restore-Free Mode for MLC STT-RAM Caches

Authors:

Muhammad Avais Qureshi,

Soontae KimAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 27, Issue 6

Pages 1465 - 1469

https://doi.org/10.1109/TVLSI.2019.2899894

Published: 01 June 2019 Publication History

Abstract

Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption, and lifetime. Moreover, technology scaling makes the read operations disturb the stored data in MLC STT-RAMs, giving rise to an issue called read disturbance (RD). Restore operations, which are required to cope with RD, further add to the problems of using MLCs. In this brief, we propose a Restore-free mode for frequently reused cache lines in MLC STT-RAMs that leverages single-step read/write operations to the MLC without the need for restore operations. Our proposed scheme in single-core (quad-core) systems, achieves a 27.4% (23%) dynamic energy reduction, a 3.7% (7%) increase in performance, and an 81% (62.5%) lifetime improvement.

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Cited By

Sivakumar SJose JNarayanan V(2024)Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace BuffersACM Transactions on Design Automation of Electronic Systems10.1145/365910229:3(1-24)Online publication date: 16-Apr-2024
https://dl.acm.org/doi/10.1145/3659102
Hsieh JHou YChang T(2022)Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311263841:8(2753-2757)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3112638
Hsieh JLiu YLee HChang T(2021)TSE: Two-Step Elimination for MLC STT-RAM Last-Level CacheIEEE Transactions on Computers10.1109/TC.2020.301436170:9(1498-1510)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1109/TC.2020.3014361
Show More Cited By

Index Terms

A Restore-Free Mode for MLC STT-RAM Caches
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 27, Issue 6

June 2019

246 pages

ISSN:1063-8210

Issue’s Table of Contents

1063-8210 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2019

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Cited By

Sivakumar SJose JNarayanan V(2024)Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace BuffersACM Transactions on Design Automation of Electronic Systems10.1145/365910229:3(1-24)Online publication date: 16-Apr-2024
https://dl.acm.org/doi/10.1145/3659102
Hsieh JHou YChang T(2022)Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM CacheIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311263841:8(2753-2757)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3112638
Hsieh JLiu YLee HChang T(2021)TSE: Two-Step Elimination for MLC STT-RAM Last-Level CacheIEEE Transactions on Computers10.1109/TC.2020.301436170:9(1498-1510)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1109/TC.2020.3014361
Wu JXu YXue BWang YLiu YYang HLi XCheng KYang H(2020)Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET MemoryProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045106(407-413)Online publication date: 17-Jan-2020
https://dl.acm.org/doi/10.1109/ASP-DAC47756.2020.9045106
Park JLee MKim SJu MHong J(2019)MH CacheACM Transactions on Architecture and Code Optimization10.1145/332852016:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3328520

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