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Scheduling techniques for variable voltage low power designs

Authors:

Yann-Rue Lin,

Cheng-Tsung Hwang,

Allen C.-H. WuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2, Issue 2

Pages 81 - 97

https://doi.org/10.1145/253052.253054

Published: 01 April 1997 Publication History

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Abstract

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.

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Cited By

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Roy Barman KBaishya S(2019)Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noiseApplied Physics A10.1007/s00339-019-2682-x125:6Online publication date: 13-May-2019
https://doi.org/10.1007/s00339-019-2682-x
Campbell KZuo WChen D(2017)New advances of high-level synthesis for efficient and reliable hardware designIntegration10.1016/j.vlsi.2016.11.00658(189-214)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2016.11.006
Yang YZhao YDong G(2015)A Multi-Output on-Chip Switched-Capacitor DC–DC Converter with Unequal Flying Capacitors for Different Power ModesJournal of Circuits, Systems and Computers10.1142/S021812661550051624:04(1550051)Online publication date: Apr-2015
https://doi.org/10.1142/S0218126615500516
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Index Terms

Scheduling techniques for variable voltage low power designs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Very large scale integration design
    1. VLSI packaging
      1. Input / output styles

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 2, Issue 2

April 1997

112 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/253052

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 1997

Published in TODAES Volume 2, Issue 2

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Roy Barman KBaishya S(2019)Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noiseApplied Physics A10.1007/s00339-019-2682-x125:6Online publication date: 13-May-2019
https://doi.org/10.1007/s00339-019-2682-x
Campbell KZuo WChen D(2017)New advances of high-level synthesis for efficient and reliable hardware designIntegration10.1016/j.vlsi.2016.11.00658(189-214)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2016.11.006
Yang YZhao YDong G(2015)A Multi-Output on-Chip Switched-Capacitor DC–DC Converter with Unequal Flying Capacitors for Different Power ModesJournal of Circuits, Systems and Computers10.1142/S021812661550051624:04(1550051)Online publication date: Apr-2015
https://doi.org/10.1142/S0218126615500516
Ni JWang NYoshimura T(2015)Tabu search based multiple voltage scheduling under both timing and resource constraintsSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085410(118-122)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085410
Chandrakar KRoy S(2015)Effect of increasing voltage levels on power saving obtained by multiple voltages design2015 IEEE International Advance Computing Conference (IACC)10.1109/IADCC.2015.7154829(867-871)Online publication date: Jun-2015
https://doi.org/10.1109/IADCC.2015.7154829
ABE SSHI YUSAMI KYANAGISAWA MTOGAWA N(2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
https://doi.org/10.1587/transfun.E96.A.2597
Hyman RRanganathan NBingel TVo D(2013)A clock control strategy for peak power and RMS current reduction using path clusteringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218698921:2(259-269)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2186989
Cong Hao Song Chen Yoshimura T(2013)Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509602(237-242)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509602
Haoran Zhang Hao CNan Wang Chen SYoshimura T(2013)Power and resource aware scheduling with multiple voltages2013 IEEE 10th International Conference on ASIC10.1109/ASICON.2013.6811931(1-4)Online publication date: Oct-2013
https://doi.org/10.1109/ASICON.2013.6811931
Abe SYanagisawa MTogawa N(2012)Energy-efficient High-level Synthesis for HDR ArchitecturesIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.5.1065(106-117)Online publication date: 2012
https://doi.org/10.2197/ipsjtsldm.5.106
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Abstract

References

Cited By

Index Terms

Recommendations

Datapath scheduling with multiple supply voltages and level converters

Scheduling and resource binding for low power

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management

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