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Variable voltage scheduling

Published: 23 April 1995 Publication History
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References

[1]
L. S. Nielsen and J. Sparso, "Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage", Proc. of the International Workshop on Low Power Design, April 1994, pp. 99-104.
[2]
L. S. Nielsen, C. Niessen, J. Sparso, and K. V. Berkel, "Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage", IEEE transactions on VLSI Systems, Vol. 2, No. 4, December 1994, pp. 391-397.
[3]
A. Chandrakasan, S. Sheng, and R. Brodersen," Lowpower CMOS Digital Design", IEEE Journal of Solidstate circuit, April 1992, pp. 473-484.
[4]
J. Monteiro, A. Devadas, and A. Ghosh, "Retiming Sequential Circuits for Low Power," Proc. of the IEEE ICCAD-93, November 1993, pp. 398-402.
[5]
M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power", IEEE transactions on VLSI Systems, Vol. 2, No. 4, December 1994, pp. 426-436.
[6]
K. Roy and S. Prasad, "SYCLOP: Synthesis of CMOS Logic for Low Power Applications", Proc. of the International Conference on Computer Design: VLSI in Computers and Processors, October 1992, pp. 464- 467.
[7]
R. A. Walker and R. Camposano, "A Survey of High- Level Synthesis Systems". Kluwer, MA, 1991.
[8]
A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, "Optimizing Power Using Transformations", Transcript of the journal paper (not yet published).

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  • (2016)Pipelining for dual supply voltages2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833419(9-16)Online publication date: Sep-2016
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cover image ACM Conferences
ISLPED '95: Proceedings of the 1995 international symposium on Low power design
April 1995
233 pages
ISBN:0897917448
DOI:10.1145/224081
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 April 1995

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LPD95
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LPD95: Low Power Design Symposium
April 23 - 26, 1995
California, Dana Point, USA

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Cited By

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  • (2017)VISUAL: Simulation of Visual Subgraph Query Formulation to Enable Automated Performance BenchmarkingIEEE Transactions on Knowledge and Data Engineering10.1109/TKDE.2017.269039229:8(1765-1778)Online publication date: 1-Aug-2017
  • (2016)Pipelining for dual supply voltages2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833419(9-16)Online publication date: Sep-2016
  • (2016)Retiming and dual-supply voltage based energy optimization for DSP applications2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)10.1109/ICASSP.2016.7471837(1055-1059)Online publication date: Mar-2016
  • (2016)Decoupling Capacitors for Multi-Voltage Power Distribution SystemsOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_42(651-674)Online publication date: 27-Apr-2016
  • (2016)On-Chip Power Grids with Multiple Supply VoltagesOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_41(619-650)Online publication date: 27-Apr-2016
  • (2015)High-level Synthesis for Low-power DesignIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.128(12-25)Online publication date: 2015
  • (2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
  • (2013)A clock control strategy for peak power and RMS current reduction using path clusteringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218698921:2(259-269)Online publication date: 1-Feb-2013
  • (2012)Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145750(268-268)Online publication date: 22-Feb-2012
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