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Power-profiler: optimizing ASICs power consumption at the behavioral level

Authors:

Raul San Martin,

John P. KnightAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 42 - 47

https://doi.org/10.1145/217474.217504

Published: 01 January 1995 Publication History

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Cited By

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Singh SGond S(2017)Green Computing and Its ImpactNature-Inspired Computing10.4018/978-1-5225-0788-8.ch062(1628-1642)Online publication date: 2017
https://doi.org/10.4018/978-1-5225-0788-8.ch062
Singh SGond S(2016)Green Computing and Its ImpactEmerging Research Surrounding Power Consumption and Performance Issues in Utility Computing10.4018/978-1-4666-8853-7.ch004(69-83)Online publication date: 2016
https://doi.org/10.4018/978-1-4666-8853-7.ch004
Dossis M(2016)Formal Design Flows for Embedded IoT HardwareComponents and Services for IoT Platforms10.1007/978-3-319-42304-3_2(27-55)Online publication date: 24-Sep-2016
https://doi.org/10.1007/978-3-319-42304-3_2
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Index Terms

Power-profiler: optimizing ASICs power consumption at the behavioral level
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 January 1995

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SIGDA

DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Singh SGond S(2017)Green Computing and Its ImpactNature-Inspired Computing10.4018/978-1-5225-0788-8.ch062(1628-1642)Online publication date: 2017
https://doi.org/10.4018/978-1-5225-0788-8.ch062
Singh SGond S(2016)Green Computing and Its ImpactEmerging Research Surrounding Power Consumption and Performance Issues in Utility Computing10.4018/978-1-4666-8853-7.ch004(69-83)Online publication date: 2016
https://doi.org/10.4018/978-1-4666-8853-7.ch004
Dossis M(2016)Formal Design Flows for Embedded IoT HardwareComponents and Services for IoT Platforms10.1007/978-3-319-42304-3_2(27-55)Online publication date: 24-Sep-2016
https://doi.org/10.1007/978-3-319-42304-3_2
Bolla RBruschi RCarrega ADavoli F(2014)Green Networking With Packet Processing EnginesIEEE/ACM Transactions on Networking10.1109/TNET.2013.224248522:1(110-123)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1109/TNET.2013.2242485
Saravanakumaran BJoseph M(2012)Survey on Optimization Techniques in High Level SynthesisAdvances in Computer Science and Information Technology. Computer Science and Engineering10.1007/978-3-642-27308-7_2(11-21)Online publication date: 2012
https://doi.org/10.1007/978-3-642-27308-7_2
Helms DNebel WPiguet C(2009)High-Level Power Estimation and AnalysisLow-Power CMOS Circuits10.1201/9781420036503.ch18(1-25)Online publication date: 9-Nov-2009
https://doi.org/10.1201/9781420036503.ch18
Bolla RBruschi RDavoli FRanieri ACrowley PMaltz DVan der Merwe K(2009)Energy-aware performance optimization for next-generation green network equipmentProceedings of the 2nd ACM SIGCOMM workshop on Programmable routers for extensible services of tomorrow10.1145/1592631.1592643(49-54)Online publication date: 21-Aug-2009
https://dl.acm.org/doi/10.1145/1592631.1592643
Yasuura HIshihara TMuroyama M(2007)Energy Management Techniques for SOC DesignEssential Issues in SOC Design10.1007/1-4020-5352-5_6(177-223)Online publication date: 2007
https://doi.org/10.1007/1-4020-5352-5_6
Lin CKim J(2006)A Novel Scheduling methodology for ASIC Design2006 6th International Workshop on System on Chip for Real Time Applications10.1109/IWSOC.2006.348222(131-134)Online publication date: Dec-2006
https://doi.org/10.1109/IWSOC.2006.348222
Wang LJiang YSelvaraj H(2006)Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply VoltagesThe Journal of Supercomputing10.1007/s11227-006-0140-y35:1(93-113)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1007/s11227-006-0140-y
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