research-article

Power-aware SoC test planning for effective utilization of port-scalable testers

Authors:

Sudarshan Bahukudumbi,

Krishnendu ChakrabartyAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13, Issue 3

Article No.: 53, Pages 1 - 19

https://doi.org/10.1145/1367045.1367062

Published: 25 July 2008 Publication History

Abstract

Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However, the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bit-width used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SoC test time. We compare the proposed heuristic optimization method to two baseline methods based on prior works that use a single scan data rate for all embedded cores. We also propose a power-aware test planning technique to effectively utilize port-scalable testers under constraints of test power consumption. Experimental results are presented for power-aware test scheduling to illustrate the impact of power constraints on overall test time.

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Cited By

Sheshadri VAgrawal VAgrawal P(2017)Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency ScalingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5652-233:2(171-187)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5652-2
Sheshadri VAgrawal VAgrawal P(2013)Power-aware SoC test optimization through dynamic voltage and frequency scaling2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673258(102-107)Online publication date: Oct-2013
https://doi.org/10.1109/VLSI-SoC.2013.6673258
Ooi CSua JLee S(2012)Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithmComputers and Electrical Engineering10.1016/j.compeleceng.2012.04.01038:6(1444-1455)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1016/j.compeleceng.2012.04.010
Show More Cited By

Index Terms

Power-aware SoC test planning for effective utilization of port-scalable testers
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 13, Issue 3

July 2008

370 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1367045

Issue’s Table of Contents

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 25 July 2008

Accepted: 01 March 2008

Revised: 01 December 2007

Received: 01 June 2007

Published in TODAES Volume 13, Issue 3

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Cited By

Sheshadri VAgrawal VAgrawal P(2017)Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency ScalingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5652-233:2(171-187)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5652-2
Sheshadri VAgrawal VAgrawal P(2013)Power-aware SoC test optimization through dynamic voltage and frequency scaling2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673258(102-107)Online publication date: Oct-2013
https://doi.org/10.1109/VLSI-SoC.2013.6673258
Ooi CSua JLee S(2012)Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithmComputers and Electrical Engineering10.1016/j.compeleceng.2012.04.01038:6(1444-1455)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1016/j.compeleceng.2012.04.010
Larsson ERavikumar C(2009)Power-Aware System-Level Test PlanningPower-Aware Testing and Test Strategies for Low Power Devices10.1007/978-1-4419-0928-2_6(175-211)Online publication date: 13-Aug-2009
https://doi.org/10.1007/978-1-4419-0928-2_6

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