Article

Test Scheduling and Scan-Chain Division under Power Constraint

Authors:

Erik Larsson,

Zebo PengAuthors Info & Claims

ATS '01: Proceedings of the 10th Asian Test Symposium

Page 259

Published: 19 November 2001 Publication History

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Abstract

An integrated technique for test scheduling and scan-chain division under power constraints is proposed in this paper. We demonstrate that optimal test time can be achieved for systems tested by an arbitrary number of tests per core using scan-chain division and we define an algorithm for it. The design of wrappers to allow different lengths of scan-chains per core is also outlined. We investigate the practical limitations of such wrapper design and make a worst case analysis that motivates our integrated test scheduling and scan-chain division algorithm. The efficiency and usefulness of our approach have been demonstrated with anindustrial design.

Cited By

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Marinissen EKapur RLousberg MMcLaurin TRicchetti MZorian Y(2019)On IEEE P1500's Standard for Embedded Core TestJournal of Electronic Testing: Theory and Applications10.1023/A:101658520609718:4-5(365-383)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1016585206097
Sinanoglu OMarinissen ESciuto D(2008)Analysis of the test data volume reduction benefit of modular SOC testingProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403421(182-187)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403421
Sehgal ABahukudumbi SChakrabarty K(2008)Power-aware SoC test planning for effective utilization of port-scalable testersACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1367045.136706213:3(1-19)Online publication date: 25-Jul-2008
https://dl.acm.org/doi/10.1145/1367045.1367062
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Index Terms

Test Scheduling and Scan-Chain Division under Power Constraint
1. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

Index terms have been assigned to the content through auto-classification.

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ATS '01: Proceedings of the 10th Asian Test Symposium

November 2001

Publisher

IEEE Computer Society

United States

Publication History

Published: 19 November 2001

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Marinissen EKapur RLousberg MMcLaurin TRicchetti MZorian Y(2019)On IEEE P1500's Standard for Embedded Core TestJournal of Electronic Testing: Theory and Applications10.1023/A:101658520609718:4-5(365-383)Online publication date: 1-Jun-2019
Sinanoglu OMarinissen ESciuto D(2008)Analysis of the test data volume reduction benefit of modular SOC testingProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403421(182-187)Online publication date: 10-Mar-2008
Sehgal ABahukudumbi SChakrabarty K(2008)Power-aware SoC test planning for effective utilization of port-scalable testersACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1367045.136706213:3(1-19)Online publication date: 25-Jul-2008
Wang (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
Wang DFan XGao DZhang SAn J(2005)Microprocessor based self schedule and parallel BIST for system-on-a-chipProceedings of the Second international conference on Embedded Software and Systems10.1007/11599555_30(299-309)Online publication date: 16-Dec-2005
Iyengar VChakrabarty KMarinissen E(2003)Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-ChipIEEE Transactions on Computers10.1109/TC.2003.125285752:12(1619-1632)Online publication date: 1-Dec-2003
Iyengar VChakrabarty KMarinissen EAckland B(2002)Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCsProceedings of the 39th annual Design Automation Conference10.1145/513918.514092(685-690)Online publication date: 10-Jun-2002

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Scan chain clustering for test power reduction

Improving test effectiveness of scan-based BIST by scan chain partitioning

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