article

Compilation for compact power-gating controls

Authors:

Chung-Wen Huang,

Jenq Kuen LeeAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12, Issue 4

Pages 51 - es

https://doi.org/10.1145/1278349.1278364

Published: 01 September 2007 Publication History

Abstract

Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.

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Index Terms

Compilation for compact power-gating controls
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Information & Contributors

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 12, Issue 4

September 2007

449 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1278349

Issue’s Table of Contents

Copyright © 2007 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 September 2007

Published in TODAES Volume 12, Issue 4

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Cited By

Lin JYang YLai HLee J(2024)Rewriting and Optimizing Vector Length Agnostic Intrinsics from Arm SVE to RVVWorkshop Proceedings of the 53rd International Conference on Parallel Processing10.1145/3677333.3678151(38-47)Online publication date: 12-Aug-2024
https://dl.acm.org/doi/10.1145/3677333.3678151
Felzmann IFilho JWanner L(2020)Risk-5: Controlled approximations for RISC-VIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012312(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012312
Ma Y(2020)Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy OptimizationIEEE Access10.1109/ACCESS.2019.29615688(1733-1754)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2019.2961568
Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Ma YChao WLiu T(2018)Enabling energy-proportional computing on instruction-level parallel processorsThe Journal of Supercomputing10.5555/2733630.273365471:2(391-447)Online publication date: 31-Dec-2018
https://dl.acm.org/doi/10.5555/2733630.2733654
Pyne S(2018)Rescheduling of Power Gating Instructions for Reduction of In-rush Current2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.32(25-30)Online publication date: Jan-2018
https://doi.org/10.1109/VLSID.2018.32
Tong YZhang WMa YLiu YLiang YZhang TLuo H(2017)Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP ProcessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263641925:4(1329-1341)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2636419
Lin CHuang CKuan CHuang SLee J(2015)The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/269983420:2(1-27)Online publication date: 2-Mar-2015
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Lin CKuan CShih WLee J(2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1007/s11265-014-0917-9
Shih WYou YHuang CLee J(2014)Compiler Optimization for Reducing Leakage Power in Multithread BSP ProgramsACM Transactions on Design Automation of Electronic Systems10.1145/266811920:1(1-34)Online publication date: 18-Nov-2014
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