Article

Location cache: a low-power L2 cache system

Authors:

Yiming HuAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 120 - 125

https://doi.org/10.1145/1013235.1013271

Published: 09 August 2004 Publication History

Abstract

While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large set-associative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache.The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly.We used the CACTI cache model to evaluate the power con-sumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is power-efficient. In the simulated cache configurations, up-to 47% of cache accessing energy and 25% of average cache access latency can be reduced.

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Cited By

Oh YChung E(2021)Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance DetectionIEEE Access10.1109/ACCESS.2021.31267399(155048-155057)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3126739
Ratnakumar RChaitanya PGurunarayanan S(2019)An Energy Efficient Multilevel Reconfigurable parallel Cache Architecture for Embedded Multicore Processors2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON47278.2019.8980197(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/UPCON47278.2019.8980197
Munir AGordon-Ross ARanka S(2016)ReferencesModeling and Optimization of Parallel and Distributed Embedded Systems10.1002/9781119086383.refs(349-368)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781119086383.refs
Show More Cited By

Index Terms

Location cache: a low-power L2 cache system
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 August 2004

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ISLPED04

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ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Citations

Cited By

Oh YChung E(2021)Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance DetectionIEEE Access10.1109/ACCESS.2021.31267399(155048-155057)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3126739
Ratnakumar RChaitanya PGurunarayanan S(2019)An Energy Efficient Multilevel Reconfigurable parallel Cache Architecture for Embedded Multicore Processors2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON47278.2019.8980197(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/UPCON47278.2019.8980197
Munir AGordon-Ross ARanka S(2016)ReferencesModeling and Optimization of Parallel and Distributed Embedded Systems10.1002/9781119086383.refs(349-368)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781119086383.refs
Sembrant AHagersten EBlack-Schaffer DYew PZhai AKeckler S(2014)The Direct-to-Data (D2D) cacheProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665694(133-144)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.5555/2665671.2665694
Sembrant AHagersten EBlack-Schaffer D(2014)The Direct-to-Data (D2D) cacheACM SIGARCH Computer Architecture News10.1145/2678373.266569442:3(133-144)Online publication date: 14-Jun-2014
https://dl.acm.org/doi/10.1145/2678373.2665694
Zheng ZWang ZLipasti MXie YKarnik TKhellah MMehra R(2014)Tag check elisionProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627606(351-356)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2627606
Munir AGordon-Ross ARanka SKoushanfar F(2014)A queueing theoretic approach for performance evaluation of low-power multi-core embedded systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2013.07.00374:1(1872-1890)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1016/j.jpdc.2013.07.003
Choi JKwak JJhang SJhon CSuen CAghdam AGuo MHong JNadimi E(2013)Data filter cache with word selection cache for low power embedded processorProceedings of the 2013 Research in Adaptive and Convergent Systems10.1145/2513228.2513258(422-427)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2513228.2513258
Dai JWang L(2013)An energy-efficient L2 cache architecture using way tag information under write-through policyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.218187921:1(102-112)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1109/TVLSI.2011.2181879
Lee JKim SHenkel JKeshavarzi AChang NGhani T(2009)An energy-delay efficient 2-level data cache architecture for embedded systemProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594318(343-346)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594318
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