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Reactive-Associative Caches

Published: 08 September 2001 Publication History

Abstract

Abstract: While set-associative caches typically incur fewer misses than direct-mapped caches, set-associative caches have slower hit times. We propose the reactive-associative cache (r-a cache), which provides flexible associativity by placing most blocks in direct-mapped positions and reactively displacing only conflicting blocks to set-associative positions. The r-a cache uses way-prediction (like the predictive associative cache, PSA) to access displaced blocks on the initial probe. Unlike PSA, however, the r-a cache employs a novel feedback mechanism to prevent unpredictable blocks from being displaced. Reactive displacement and feedback allow the r-a cache to use a novel PC-based way-prediction and achieve high accuracy; without impractical block swapping as in column associative and group associative, and without relying on timing-constrained XOR way prediction. A one-port, 4-way r-a cache achieves up to 9% speedup over a direct-mapped cache and performs within 2% of an idealized 2-way set-associative, 1-cycle cache. A 4-way r-a cache achieves up to 13% speedup over a PSA cache, with both r-a and PSA using the PC scheme. CACTI estimates that for sizes larger than 8KB, a 4-way r-a cache is within 1% of direct-mapped hit times, and 24% faster than a 2-way set-associative cache.

Cited By

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  • (2018)ACCORDProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00036(328-339)Online publication date: 2-Jun-2018
  • (2014)Tag check elisionProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627606(351-356)Online publication date: 11-Aug-2014
  • (2013)TLCProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540714(49-61)Online publication date: 7-Dec-2013
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cover image ACM Conferences
PACT '01: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
September 2001
188 pages
ISBN:0769513638

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IEEE Computer Society

United States

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Published: 08 September 2001

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

View all
  • (2018)ACCORDProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00036(328-339)Online publication date: 2-Jun-2018
  • (2014)Tag check elisionProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627606(351-356)Online publication date: 11-Aug-2014
  • (2013)TLCProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540714(49-61)Online publication date: 7-Dec-2013
  • (2012)Reducing L1 caches power by exploiting software semanticsProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333750(391-396)Online publication date: 30-Jul-2012
  • (2011)Selective word reading for high performance and low power processorProceedings of the 2011 ACM Symposium on Research in Applied Computation10.1145/2103380.2103386(25-30)Online publication date: 2-Nov-2011
  • (2011)Architecting high-performance energy-efficient soft error resilient cache under 3D integration technologyMicroprocessors & Microsystems10.1016/j.micpro.2011.01.00435:4(371-381)Online publication date: 1-Jun-2011
  • (2010)Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded systemProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785542(257-262)Online publication date: 16-May-2010
  • (2009)Way guardProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594276(165-170)Online publication date: 19-Aug-2009
  • (2008)Word-interleaved cacheProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393991(265-270)Online publication date: 11-Aug-2008
  • (2008)Reconfigurable energy efficient near threshold cache architecturesProceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2008.4771813(459-470)Online publication date: 8-Nov-2008
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