Article

Exploiting temporal locality in drowsy cache policies

Authors:

Salvador Petit,

Julio Sahuquillo,

David KaeliAuthors Info & Claims

CF '05: Proceedings of the 2nd conference on Computing frontiers

Pages 371 - 377

https://doi.org/10.1145/1062261.1062321

Published: 04 May 2005 Publication History

Abstract

Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage of the overall microprocessor die area. Therefore, recent research has concentrated on the reduction of leakage current dissipated by caches. The variety of techniques to control current leakage can be classified as non-state preserving or state preserving. Non-state preserving techniques power off selected cache lines while state preserving place selected lines into a low-power state. Drowsy caches are a recently proposed state-preserving technique. In order to introduce low performance overhead, drowsy caches must be very selective on which cache lines are moved to a drowsy statePast research on cache organization has focused on how best to exploit the temporal locality present in the data stream. In this paper we propose a novel drowsy cache policy called Reuse Most Recently used On (RMRO), which makes use of reuse information to trade off performance versus energy consumption. Our proposal improves the hit ratio for drowsy lines by about 67%, while reducing the power consumption by about 11.7% (assuming 70nm technology) with respect to previously proposed drowsy cache policies.

References

[1]

Albonesi, D. H. Selective Cache Ways: On-Demand Cache Resource Allocation. Journal of Instruction-Level Parallelism, Vol. 2, 2000.

[2]

Burger, D. C. and Austin, T. M. The SimpleScalar Tool Set, Version 2.0. Computer Architecture News, 25 (3), 1997.

Digital Library

[3]

Chen, C., Yang, S-H., Falsafi, B., and Moshovos, A. Accurate and Complexity-Effective Spatial Pattern Prediction. Proc. of the 10th Intl. Symp. on High Performance Computer Architecture, Feb. 2004.

Digital Library

[4]

Dropsho, S., Kursun, V., Albonesi, D. H., Dwarkadas, S., and Friedman, E. G. Managing Static Leakage Energy in Microprocessor Functional Units. Proc. of the 35th Intl. Symp. on Microarchitecture, Nov. 2002.

Digital Library

[5]

Flautner, K., Kim, N. S., Martin, S., Blaauw, D., and Mudge, T. Drowsy Caches: Simple Techniques for Reducing Leakage Power. Proc. of the 29th Intl. Symp. on Computer Architecture, May 2002.

Digital Library

[6]

Kaxiras, S., HU, Z., and Martonosi, M. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. Proc. of the 28th Intl. Symp. on Computer Architecture, Jun. 2001.

Digital Library

[7]

Kessler, R. E. The Alpha 21264 Microprocessor. IEEE Micro, Vol. 19, No. 2, Mar. 1999.

Digital Library

[8]

KleinOsowski, A. J. and Lilja, D. J. MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. Computer Architecture Letters, Vol. 1, Jun. 2002.

Digital Library

[9]

Li, L., Kadayif, I., Tsai, Y-F., Vijaykrishnan, N., Kandemir, M., Irwin, M. J., and Sivasubramania, A. Leakage Energy Management in Cache Hierarchies. Proc. of the 11th Intl. Conf. on Parallel Architectures and Compilation Techniques, Sep. 2002.

Digital Library

[10]

Li, Y., Parikh, D., Zhang, Y., Sankaranarayanan, K., Stan, M. R., and Skadron, K. State-Preserving vs. Non-State-Preserving Leakage Control in Caches. Proc. of the 2004 Design, Automation and Test in Europe Conf., Feb. 2004.

Digital Library

[11]

McNairy, C. and Soltis, D. Itanium 2 Processor Microarchitecture. IEEE Micro, Vol. 23, No. 2, Mar.-Apr. 2003.

Digital Library

[12]

Powell, M., Yang, S.-H., Falsafi, B., Roy, K., and Vijaykumar, T. N. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. Proc. of the 2000 Intl. Symp. on Low Power Electronics and Design, Jul. 2000.

Digital Library

[13]

SIA, International Technology Roadmap for Semiconductors, 2001.

[14]

Standard Performance Evaluation Corporation. http://www.spec.org/cpu2000/

[15]

Tam, E. S., Rivers, J. A., Srinivasan, V., Tyson, G. S., and Davidson, E. S. Active Management of Data Caches by Exploiting Reuse Information. IEEE Transactions on Computers, Vol. 48, No. 11, Nov. 1999.

Digital Library

[16]

Zhang, Y., Parikh, D., Sankaranarayanan, K., Skadron, K., Stan, M. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Tech. Report CS-2003-05, Dept. of Electrical and Computer Engineering, Univ. of Virginia, Mar. 2003.

Cited By

Hu SHaung J(2019)Exploring Adaptive Cache for Reconfigurable VLIW ProcessorIEEE Access10.1109/ACCESS.2019.29195897(72634-72646)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2919589
Puche JPetit SSahuquillo JGómez M(2019)FOS: a low-power cache organization for multicoresThe Journal of Supercomputing10.1007/s11227-019-02858-xOnline publication date: 24-Apr-2019
https://doi.org/10.1007/s11227-019-02858-x
Lopez SNimkar YKotas G(2018)How Much Cache is Enough? A Cache Behavior Analysis for Machine Learning GPU Architectures2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752137(1-5)Online publication date: Oct-2018
https://doi.org/10.1109/IGCC.2018.8752137
Show More Cited By

Index Terms

Exploiting temporal locality in drowsy cache policies
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Recommendations

Location cache: a low-power L2 cache system
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which ...
A buffer cache management scheme exploiting both temporal and spatial localities

On-disk sequentiality of requested blocks, or their spatial locality, is critical to real disk performance where the throughput of access to sequentially-placed disk blocks can be an order of magnitude higher than that of access to randomly-placed ...
Application-adaptive intelligent cache memory system

This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

CF '05: Proceedings of the 2nd conference on Computing frontiers

May 2005

467 pages

ISBN:1595930191

DOI:10.1145/1062261

General Chair:
Nader Bagherzadeh,
Program Chairs:
Mateo Valero,
Alex Ramirez

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 May 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

CF05

Sponsor:

CF05: Computing Frontiers Conference

May 4 - 6, 2005

Ischia, Italy

Acceptance Rates

Overall Acceptance Rate 273 of 785 submissions, 35%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

31
Total Citations
View Citations
372
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 02 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hu SHaung J(2019)Exploring Adaptive Cache for Reconfigurable VLIW ProcessorIEEE Access10.1109/ACCESS.2019.29195897(72634-72646)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2919589
Puche JPetit SSahuquillo JGómez M(2019)FOS: a low-power cache organization for multicoresThe Journal of Supercomputing10.1007/s11227-019-02858-xOnline publication date: 24-Apr-2019
https://doi.org/10.1007/s11227-019-02858-x
Lopez SNimkar YKotas G(2018)How Much Cache is Enough? A Cache Behavior Analysis for Machine Learning GPU Architectures2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752137(1-5)Online publication date: Oct-2018
https://doi.org/10.1109/IGCC.2018.8752137
Jatala VAnantpur JKarkare A(2018)Reducing GPU Register File EnergyEuro-Par 2018: Parallel Processing10.1007/978-3-319-96983-1_6(77-91)Online publication date: 1-Aug-2018
https://doi.org/10.1007/978-3-319-96983-1_6
Wang PChen T(2017)Reducing Timing Discrepancy for Energy-Efficient On-Chip Memory Architectures at Low-Voltage ModeSmart Sensors at the IoT Frontier10.1007/978-3-319-55345-0_4(73-106)Online publication date: 31-May-2017
https://doi.org/10.1007/978-3-319-55345-0_4
Wang PCheng WYu YKao TTsai CChang PLin TWang JChen T(2016)Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient OperationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.253903863:10(969-973)Online publication date: Oct-2016
https://doi.org/10.1109/TCSII.2016.2539038
Wang PTsai STanjung RLin TWang JChen T(2016)Cross-matching cachesIntegration, the VLSI Journal10.1016/j.vlsi.2016.01.00154:C(24-36)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2016.01.001
Kenyon SAlarcon SSahuquillo J(2015)Impact of Partitioning Cache Schemes on the Cache Hierarchy of SMT ProcessorsProceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and Systems10.1109/HPCC-CSS-ICESS.2015.127(706-711)Online publication date: 24-Aug-2015
https://dl.acm.org/doi/10.1109/HPCC-CSS-ICESS.2015.127
Valero APetit SSahuquillo JKaeli DDuato J(2015)A reuse-based refresh policy for energy-aware eDRAM cachesMicroprocessors & Microsystems10.1016/j.micpro.2014.12.00139:1(37-48)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1016/j.micpro.2014.12.001
Lorente VValero APetit SFoglia PSahuquillo J(2014)Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant CachesProceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.10(19-26)Online publication date: 20-Aug-2014
https://dl.acm.org/doi/10.1109/HPCC.2014.10
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents