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Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration

Published: 06 June 2019 Publication History

Abstract

In this paper, we consider dynamic overlays which use fine-grained partial reconfiguration (PR) to continuously adapt to their software-based workload. In particular, we show how to modify a traditional (static) overlay developed for OpenVX into a dynamic overlay. We use a Xilinx FPGA, and show that the dynamic overlay needs unsupported features including faster PR, relocatability, and fine-grained configuration is needed for performance. Since these features are not available in Xilinx FPGAs, we estimate the application-level speedup they would provide. We find that vector custom instruction (VCI) chaining, which allow a VCI to directly cascade its result into another VCI is also essential. Overall, we find the static overlay achieves a speedup of roughly 20x faster than a Cortex-A9 processor, but with improved PR and chaining a speedup of 106x is attainable. While there have been calls for fast, fine-grained PR devices for decades, we believe that dynamic overlays may be the first true "killer application" that will justify adding these features to all FPGA devices.

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Cited By

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  • (2020)Partial Reconfiguration for Design Optimization2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00061(328-334)Online publication date: Aug-2020

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Published In

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HEART '19: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies
June 2019
106 pages
ISBN:9781450372558
DOI:10.1145/3337801
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 2019

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HEART 2019

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HEART '19 Paper Acceptance Rate 12 of 29 submissions, 41%;
Overall Acceptance Rate 22 of 50 submissions, 44%

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  • (2020)Partial Reconfiguration for Design Optimization2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00061(328-334)Online publication date: Aug-2020

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