panel

Extreme parallel architectures for the masses

Authors:

Tarek El-Ghazawi,

Guy LemieuxAuthors Info & Claims

FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Pages 127 - 128

https://doi.org/10.1145/1344671.1344691

Published: 24 February 2008 Publication History

Get Access

Abstract

Multicore processors are now commodity items, and this has created an unprecedented buzz about exploiting parallelism to maximize performance. This is publicity has renewed interest in a long-standing problem: how much parallelism can we really exploit? Can extreme parallel computing be successfully delivered to the masses?

Today, we have three commercially-available solutions to exploit vast amounts of parallelism: FPGAs, GPUs, and the Cell processor. All of these architectures share the advantage of being in mass production, so they offer the promise of making extreme parallel computing available to mainstream markets. Plus, there are new architectures on the horizon to support extreme parallelism located in research labs and in startup companies in the form of coarse-grain reconfigurable arrays and stream processors.

Each of these architectures boasts orders of magnitude speedup on particular applications. For example, FPGAs excel at situations where customization helps: bit-level operations, deep dataflow graphs with complex communication patterns, and highly flexible on-chip buffering and memory architecture. In contrast, GPUs excel at streaming operations that match their deep, multi-threaded pipelines while the Cell offers multiple high-speed, independent SIMD pipelines. Coarse-grain arrays can exploit both fine and coarse levels of parallelism, while stream processors excel at signal processing tasks

Which of these architectures is the best approach for exploiting large amounts of parallelism? For a given application, how does one decide which approach will give the best results?

All of these approaches work extremely well in their intended application domain. However, they all strive to become more general-purpose in nature. Which ones will win out in the long run? What are the main obstacles standing in their path?

Index Terms

Extreme parallel architectures for the masses
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints

Recommendations

A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
DSD '15: Proceedings of the 2015 Euromicro Conference on Digital System Design

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required ...
Designing with extreme parallelism
FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Modern FPGAs can implement large, custom compute engines that are designed to exploit extreme amounts of parallel computation. Through parallelism, these systems achieve orders of magnitude higher performance than the fastest microprocessors. Building ...
SAccO

This paper presents SAccO (Scalable Accelerator platform Osnabrück), a novel framework for implementing data-intensive applications using scalable and portable reconfigurable hardware accelerators. Instead of using expensive "reconfigurable ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

February 2008

278 pages

ISBN:9781595939340

DOI:10.1145/1344671

General Chair:
Mike Hutton
Altera, USA
,
Program Chair:
Paul Chow
University of Toronto, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2008

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Panel

Conference

FPGA08

Sponsor:

FPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 24 - 26, 2008

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

0
Total Citations
280
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Nov 2024

Other Metrics

View Author Metrics

Citations

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Index Terms

Recommendations

A Many-Core Co-Processor for Embedded Parallel Computing on FPGA

Designing with extreme parallelism

SAccO