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Hadi Parandeh-Afshar
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2010 – 2019
- 2018
- [c23]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
, Siamak Mohammadi
Exploration of approximate multipliers design space using carry propagation free compressors. ASP-DAC 2018: 611-616 - [c22]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
Approximate quaternary addition with the fast carry chains of FPGAs. DATE 2018: 577-580 - 2017
- [c21]Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. DFT 2017: 1-6 - 2014
- [c20]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - 2013
- [c19]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c18]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - 2012
- [b1]Hadi Parandeh-Afshar:
Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency. EPFL, Switzerland, 2012 - [c17]Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne:
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA 2012: 119-128 - [c16]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - 2011
- [j5]Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(4): 39:1-39:19 (2011) - [c15]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 - [c14]Hadi Parandeh-Afshar, Paolo Ienne:
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL 2011: 225-231 - 2010
- [j4]Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c13]Hadi Parandeh-Afshar, Paolo Ienne:
Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM 2010: 229-236 - [c12]Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24
2000 – 2009
- 2009
- [j3]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [j2]Hadi Parandeh-Afshar, Philip Brisk
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2(3): 19:1-19:42 (2009) - [c11]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c10]Hadi Parandeh-Afshar, Philip Brisk
Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249 - [c9]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c8]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - 2008
- [c7]Hadi Parandeh-Afshar, Philip Brisk
Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 - [c6]Hadi Parandeh-Afshar, Philip Brisk
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 - [c5]Hadi Parandeh-Afshar, Philip Brisk
A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 - [c4]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - 2007
- [j1]Hadi Parandeh-Afshar, Mohsen Saneei
Fast INC-XOR codec for low-power address buses. IET Comput. Digit. Tech. 1(5): 625-626 (2007) - [c3]Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 - 2006
- [c2]Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari
A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor. ICECS 2006: 119-122 - [c1]Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz:
A very high performance address BUS encoder. ISCAS 2006
Coauthor Index
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