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Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling

Published: 25 January 2017 Publication History

Abstract

Implementing cost effective congestion control within the Network-on-Chip (NoC) is a major design challenge. Whenever congestion awareness and/or mitigation is desired, architects typically rely on the use of adaptive routing algorithms, which aim to (intelligently) balance the traffic load throughout the NoC. Nevertheless, the hardware cost incurred by such solutions is quite considerable, since it entails the collection/propagation of traffic-related information and the provisioning of deadlock freedom guarantees. In this paper, we explore the potential of simultaneous edge and in-network traffic throttling, as a low-cost alternative to adaptive routing techniques. Without any reliance on adaptivity by the routing algorithm, combined throttling is demonstrated to yield better (in most cases) throughput improvements than state-of-the-art adaptive routing algorithms, but at a significantly lower cost.

References

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N. Agarwal, T. Krishna, L. S. Peh, and N. K. Jha. Garnet: A detailed on-chip network model inside a full-system simulator. In ISPASS '09, 2009.
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E. Baydal, P. Lopez, and J. Duato. A family of mechanisms for congestion control in wormhole networks. IEEE Transactions on Parallel and Distributed Systems, 16(9), Sept 2005.
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P. Gratz, B. Grot, and S. W. Keckler. Regional congestion awareness for load balance in networks-on-chip. In HPCA '08, 2008.
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T. Krishna, L.-S. Peh, B. M. Beckmann, and S. K. Reinhardt. Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. In MICRO '11, pages 71--82, 2011.
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U. Y. Ogras and R. Marculescu. Prediction-based flow control for network-on-chip traffic. In DAC '06, 2006.
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L.-S. Peh and W. J. Dally. A delay model and speculative architecture for pipelined routers. In HPCA '01, 2001.
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M. Ramakrishna, P. V. Gratz, and A. Sprintson. Gca: Global congestion awareness for load balance in networks-on-chip. In NoCS '13, 2013.
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Cited By

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  • (2019)Detection and Analysis of Congestion of Nodes in Many-Core ProcessorFirst International Conference on Sustainable Technologies for Computational Intelligence10.1007/978-981-15-0029-9_59(755-768)Online publication date: 2-Nov-2019

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    AISTECS '17: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems
    January 2017
    49 pages
    ISBN:9781450352260
    DOI:10.1145/3073763
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 25 January 2017

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    Author Tags

    1. congestion management
    2. low-cost architecture
    3. multi-core
    4. network-on-chip

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    AISTECS '17

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    AISTECS '17 Paper Acceptance Rate 7 of 8 submissions, 88%;
    Overall Acceptance Rate 7 of 8 submissions, 88%

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    • (2019)Detection and Analysis of Congestion of Nodes in Many-Core ProcessorFirst International Conference on Sustainable Technologies for Computational Intelligence10.1007/978-981-15-0029-9_59(755-768)Online publication date: 2-Nov-2019

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