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Costas Efstathiou
Constantinos Efstathiou
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2020 – today
- 2023
- [j26]Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos:
On the modulo 2n+1 addition and subtraction for weighted operands. Microprocess. Microsystems 101: 104897 (2023) - 2022
- [c60]Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas
:
Efficient Dynamic Logic Magnitude Comparators. VLSI-SoC 2022: 1-5 - 2021
- [j25]Constantinos Efstathiou, Paris Kitsos
Efficient majority logic magnitude comparator design. Microprocess. Microsystems 82: 103832 (2021) - 2020
- [j24]Fotios Ntouskas, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Efficient design of magnitude and 2's complement comparators. Integr. 71: 164-169 (2020) - [j23]Constantinos Efstathiou
On the Diminished-1 Modulo 2n+1 Addition and Subtraction. J. Circuits Syst. Comput. 29(5): 2030005:1-2030005:14 (2020)
2010 – 2019
- 2019
- [c59]Costas Efstathiou, Yiorgos Tsiatouhas
On the Static CMOS Implementation of Magnitude Comparators. PATMOS 2019: 103-106 - 2018
- [c58]Ioannis Voyiatzis, Costas Efstathiou:
SIC pair generation in near-optimal time with carry-look ahead adders. DTIS 2018: 1-2 - [c57]Ioannis Voyiatzis, Constantinos Efstathiou, Cleo Sgouropoulou
Programmable logic for single-output functions. DTIS 2018: 1-2 - [c56]Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas
Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS 2018: 249-252 - 2017
- [c55]Ioannis Voyiatzis, Costas Efstathiou:
On the generation of binary functions with low-overhead. DTIS 2017: 1-2 - 2016
- [c54]Kiamal Z. Pekmestzi, Constantinos Efstathiou:
Design of Efficient 1's Complement Modified Booth Multiplier. DSD 2016: 238-243 - [c53]Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou:
Fused modulo 2n + 1 add-multiply unit for weighted operands. DTIS 2016: 1-6 - [c52]Ioannis Voyiatzis, Costas Efstathiou, Kiriakos Patriarcheas:
Software-based SIC pair Generation. PCI 2016: 59 - [c51]Ioannis Voyiatzis, Costas Efstathiou:
Low Cost Boolean Function generation. PCI 2016: 62 - 2015
- [c50]Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos, K. Vlahantonis, P. Kyrkos, Cleo Sgouropoulou
Test set embedding into hardware generated sequences using an embedding algorithm. DTIS 2015: 1-2 - [c49]Ioannis Voyiatzis, Cleo Sgouropoulou
A concurrent BIST scheme for read only memories. DTIS 2015: 1-2 - [c48]Ioannis Voyiatzis, Cleo Sgouropoulou
Detecting untestable hardware Trojan with non-intrusive concurrent on line testing. DTIS 2015: 1-2 - [c47]Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis:
Modulo 2n ± 1 Fused Add-Multiply Units. ISVLSI 2015: 91-96 - [c46]Ioannis Voyiatzis, Costas Efstathiou:
On the use of hard faults to generate test sets. Panhellenic Conference on Informatics 2015: 92-93 - [c45]Ioannis Voyiatzis, Costas Efstathiou:
Accumulator-based generation for serial TPG. Panhellenic Conference on Informatics 2015: 426-430 - 2014
- [j22]Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding. Integr. 47(1): 140-147 (2014) - [j21]Kostas Tsoumanis, Sotirios Xydis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi:
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1133-1143 (2014) - [j20]Ioannis Voyiatzis, Costas Efstathiou:
Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1625-1629 (2014) - [c44]Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis:
On the design of efficient modulo 2n+1 multiply-add-add units. DTIS 2014: 1-4 - [c43]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs. DTIS 2014: 1-6 - [c42]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Low overhead output response compaction in RAS architectures. DTIS 2014: 1-3 - [c41]Kostas Tsoumanis, Kiamal Z. Pekmestzi, Constantinos Efstathiou:
Fused modulo 2n - 1 add-multiply unit. ICECS 2014: 40-43 - [c40]Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou:
High performance MAC designs. IDT 2014: 30-35 - [c39]Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Modulo 2n+1 addition and multiplication for redundant operands. IDT 2014: 205-210 - [c38]I. Nikopoulos, Athanasios Milidonis, Costas Efstathiou, Cleo Sgouropoulou
Stealth Assessment of Hardware Trojans in simple Processors. Panhellenic Conference on Informatics 2014: 33:1-33:5 - 2013
- [j19]Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis:
An effective two-pattern test generator for Arithmetic BIST. Comput. Electr. Eng. 39(2): 398-409 (2013) - [j18]Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi:
On the design of modulo 2n + 1 dot product and generalized multiply-add units. Comput. Electr. Eng. 39(2): 410-419 (2013) - [j17]Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas
New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 667-671 (2013) - [c37]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Symmetric transparent online BIST for arrays of word-organized RAMs. DTIS 2013: 122-127 - [c36]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Embedding test vectors in accumulator - based TPG using progressive search. DTIS 2013: 169-170 - [c35]Kiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis:
Efficient modulo 2n+1 multiplication for the idea block cipher. ACM Great Lakes Symposium on VLSI 2013: 263-268 - [c34]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Transparent testing for intra-word memory faults. IDT 2013: 1-2 - [c33]Ioannis Voyiatzis, Stelios Neophytou
Test set embedding into accumulator-generated sequences targeting hard-to-detect faults. IDT 2013: 1-2 - [c32]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
A low-cost input vector monitoring concurrent BIST scheme. IOLTS 2013: 179-180 - [c31]Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi:
On the design of modulo 2n±1 residue generators. VLSI-SoC 2013: 33-38 - 2012
- [j16]Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis:
Arithmetic module-based built-in self test architecture for two-pattern testing. IET Comput. Digit. Tech. 6(4): 195-204 (2012) - [c30]Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
On the Design of Configurable Modulo 2n±1 Residue Generators. DSD 2012: 50-56 - [c29]Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou
ALU based address generation for RAMs. DTIS 2012: 1-6 - [c28]Ioannis Voyiatzis, Costas Efstathiou, Dimitris Magos, Cleo Sgouropoulou
Test set embedding into low-power sequences based on a traveling salesman problem formulation. DTIS 2012: 1-6 - [c27]Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Test vector embedding in accumulators with stored carry in O(1) time. DTIS 2012: 1-6 - [c26]Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas
A novel architecture to reduce test time in march-based SRAM tests. DTIS 2012: 1-6 - [c25]Ioannis Voyiatzis, Kyriakos Axiotis, Nikolaos S. Papaspyrou
Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching. Panhellenic Conference on Informatics 2012: 74-79 - 2011
- [c24]Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos:
On the Design of Modulo 2^n+1 Multipliers. DSD 2011: 453-459 - [c23]Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou:
A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. ETS 2011: 206 - 2010
- [j15]Haridimos T. Vergos, Dimitris Bakalis
Fast modulo 2n+1 multi-operand adders and residue generators. Integr. 43(1): 42-48 (2010) - [j14]Ioannis Voyiatzis, Costas Efstathiou:
An efficient architecture for accumulator-based test generation of SIC pairs. Microelectron. J. 41(8): 487-493 (2010) - [c22]Costas Efstathiou:
Efficient modulo 2N+1 subtractors for weighted operands. ICECS 2010: 1-4 - [c21]Dimitris J. Kavvadias, S. Sinitos, Ioannis Voyiatzis, Hera Antonopoulou, Costas Efstathiou:
On Embedding Test Sets into Hardware Generated Sequences. Panhellenic Conference on Informatics 2010: 158-163
2000 – 2009
- 2009
- [j13]Haridimos T. Vergos, Costas Efstathiou:
Efficient modulo 2n+1 adder architectures. Integr. 42(2): 149-157 (2009) - 2008
- [j12]Haridimos T. Vergos, Costas Efstathiou:
A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1041-1045 (2008) - [c20]Haridimos T. Vergos, Dimitris Bakalis
Efficient modulo 2n + 1 multi-operand adders. ICECS 2008: 694-697 - 2007
- [j11]Haridimos T. Vergos, Costas Efstathiou:
Design of efficient modulo 2n+1 multipliers. IET Comput. Digit. Tech. 1(1): 49-57 (2007) - [j10]Themistoklis Haniotakis, Y. Tsiatouhas
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 461-465 (2007) - [c19]Athanasios P. Kakarountas
Implementation of HSSec: a high-speed cryptographic co-processor. ETFA 2007: 625-631 - [c18]Nicolas Sklavos
SecurID Authenticator: On the Hardware Implementation Efficiency. ICECS 2007: 589-592 - 2006
- [c17]Haridimos T. Vergos, Costas Efstathiou:
Novel Modulo 2n + 1 Multipliers. DSD 2006: 168-175 - 2005
- [j9]Haridimos T. Vergos, Costas Efstathiou:
On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. 14(5): 965-972 (2005) - [j8]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005) - [c16]Giorgos Dimitrakopoulos
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - 2004
- [j7]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004) - [j6]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004) - [c15]Haridimos T. Vergos, Costas Efstathiou:
Diminished-1 Modulo 2n + 1 Squarer Design. DSD 2004: 380-386 - 2003
- [j5]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003) - [j4]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003) - [c14]Giorgos Dimitrakopoulos
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336 - [c13]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos
Efficient modulo 2n+1 tree multipliers for diminished-1 operands. ICECS 2003: 200-203 - [c12]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c11]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. ISCAS (5) 2003: 225-228 - [c10]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - [c9]K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou:
A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks. MMNS 2003: 259-271 - 2002
- [j3]Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002) - [c8]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Ling adders in CMOS standard cell technologies. ICECS 2002: 485-488 - 2001
- [c7]Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217 - [c6]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
On the design of modulo 2n±1 adders. ICECS 2001: 517-520 - [c5]Y. Tsiatouhas
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 - [c4]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247 - 2000
- [j2]Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000) - [c3]Costas Efstathiou, Haridimos T. Vergos:
Modified Booth 1's complement and modulo 2n-1 multipliers. ICECS 2000: 637-640 - [c2]Th. Haniotakis, Y. Tsiatouhas
On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304
1990 – 1999
- 1990
- [j1]Antonis M. Paschalis
An Efficient TSC 1-out-of-3 Code Checker. IEEE Trans. Computers 39(3): 407-411 (1990)
1980 – 1989
- 1984
- [c1]Costas Efstathiou, Constantine Halatsis:
Modular design of totally self-checking checkers for 1-out-of-n codes. Fehlertolerierende Rechensysteme 1984: 164-176
Coauthor Index
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