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Rahul Shrestha
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2020 – today
- 2024
- [j31]Shakti Singh
, Rahul Shrestha
A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 262-273 (2024) - [j30]Elivander J. T. Pereira
VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2348-2361 (2024) - [j29]Md. Najrul Islam
Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3189-3202 (2024) - [j28]Anuj Verma
High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4284-4297 (2024) - [j27]Shakti Singh
Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion-Based Cooperative Cognitive-Radio Network. IEEE Trans. Consumer Electron. 70(1): 216-226 (2024) - [c27]Md. Najrul Islam
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator. VLSID 2024: 210-215 - 2023
- [j26]Rahul Sharma
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1298-1310 (2023) - [j25]Anuj Verma
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes. IEEE Trans. Veh. Technol. 72(1): 66-80 (2023) - [j24]Dayan Adionel Guimarães
Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks. IEEE Trans. Veh. Technol. 72(9): 11898-11912 (2023) - [c26]Meghvern Pathak, Rahul Shrestha:
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. VLSID 2023: 1-6 - 2022
- [j23]Sumanth Gudaparthi, Rahul Shrestha:
Selective register-file cache: an energy saving technique for embedded processor architecture. Des. Autom. Embed. Syst. 26(2): 105-124 (2022) - [j22]Rohit B. Chaurasiya
Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network. IEEE Trans. Consumer Electron. 68(3): 221-235 (2022) - [j21]Rohit B. Chaurasiya
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 166-176 (2022) - [j20]Rahul Sharma, Rahul Shrestha
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1020-1033 (2022) - [j19]Md. Najrul Islam
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 30(12): 1891-1901 (2022) - [j18]Lalit Kumar, Rahul Shrestha
A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal. J. Signal Process. Syst. 94(12): 1395-1410 (2022) - [c25]Kumari Suravi, Rahul Shrestha:
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems. ISVLSI 2022: 206-211 - [c24]Md. Najrul Islam
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications. ISVLSI 2022: 414-417 - 2021
- [j17]Rohit B. Chaurasiya
Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1198-1202 (2021) - [j16]Anuj Verma
Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2835-2839 (2021) - [j15]Rahul Shrestha
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 65-75 (2021) - [j14]Rohit B. Chaurasiya
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 760-773 (2021) - [c23]Rohit B. Chaurasiya, Rahul Shrestha:
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network. ISCAS 2021: 1-5 - 2020
- [j13]Rohit B. Chaurasiya
Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1296-1308 (2020) - [c22]Rahul Shrestha, Shubham Sanjay Telgote:
A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network. ISCAS 2020: 1-5 - [c21]Anuj Verma
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard. ISCAS 2020: 1-5 - [c20]Anuj Verma
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. VLSID 2020: 1-6
2010 – 2019
- 2019
- [j12]Rahul Shrestha
High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1144-1148 (2019) - [j11]Rohit B. Chaurasiya
Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4448-4461 (2019) - [c19]Rohit B. Chaurasiya, Rahul Shrestha:
Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio. ISCAS 2019: 1-5 - [c18]Rahul Shrestha, Pooja Bansal, Srikant Srinivasan
High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. VLSID 2019: 329-334 - 2018
- [j10]Mahesh S. Murty, Rahul Shrestha:
Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network. IET Circuits Devices Syst. 12(5): 542-550 (2018) - [j9]Mahesh S. Murty, Rahul Shrestha:
Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1039-1043 (2018) - [c17]Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi
Parameterized Posit Arithmetic Hardware Generator. ICCD 2018: 334-341 - [c16]Rahul Shrestha, Ashutosh Sharma:
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices. VDAT 2018: 37-48 - [c15]Rahul Shrestha, Ashutosh Sharma:
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. VLSI-SoC 2018: 131-136 - [c14]Mahesh S. Murty, Rahul Shrestha:
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. VLSID 2018: 277-282 - 2017
- [j8]Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury:
PGMA: An algorithmic approach for multi-objective hardware software partitioning. Microprocess. Microsystems 54: 83-96 (2017) - [c13]B. Dinesh Kumar
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector. ISED 2017: 1-5 - [c12]Rahul Kurzekar, Hardik Arora, Rahul Shrestha:
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform. iNIS 2017: 6-10 - [c11]Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury:
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. VDAT 2017: 62-68 - [c10]Sumanth Gudaparthi, Rahul Shrestha:
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization. VDAT 2017: 299-312 - [c9]Rahul Shrestha:
High-speed and low-power VLSI-architecture for inexact speculative adder. VLSI-DAT 2017: 1-4 - 2016
- [j7]Rahul Shrestha, Roy Paily
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. Circuits Syst. Signal Process. 35(8): 2832-2854 (2016) - [j6]Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. IET Circuits Devices Syst. 10(2): 111-120 (2016) - [c8]Mahesh S. Murty, Rahul Shrestha:
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation. ISVLSI 2016: 69-74 - [c7]Rahul Shrestha, Vinay Swargam, Mahesh S. Murty:
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives. VDAT 2016: 1-6 - [c6]Rahul Shrestha, Utkarsh Rastogiy:
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. VLSID 2016: 599-600 - 2015
- [j5]Rahul Shrestha, Roy P. Paily
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. J. Low Power Electron. 11(3): 406-412 (2015) - [j4]Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1421-1430 (2015) - [j3]Rahul Shrestha, Roy P. Paily
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. J. Signal Process. Syst. 81(2): 305-320 (2015) - [c5]John W. Burris, Rahul Shrestha, Bibek Gautam, Bibidh Bista:
Machine learning for the activation of contraflows during hurricane evacuation. GHTC 2015: 254-258 - 2014
- [j2]Rahul Shrestha, Roy P. Paily
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2699-2710 (2014) - [c4]Rahul Shrestha, Roy Paily
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. ISED 2014: 171-175 - 2013
- [j1]Rahul Shrestha, Roy P. Paily
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. IET Commun. 7(12): 1211-1220 (2013) - [c3]Rahul Shrestha, Roy P. Paily
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. ICACCI 2013: 903-907 - [c2]Rahul Shrestha, Roy P. Paily
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. VLSI Design 2013: 86-91 - 2012
- [c1]Rahul Shrestha, Roy P. Paily
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. VDAT 2012: 30-39
Coauthor Index
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last updated on 2024-10-07 22:15 CEST by the dblp team
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