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Roy P. Paily
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2020 – today
- 2024
- [j25]Titu Mary Ignatius
, Thockchom Birjit Singha
Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications. IEEE Access 12: 150230-150248 (2024) - [j24]Thockchom Birjit Singha, Basa Sanjana, Titu Mary Ignatius, Roy Paily Palathinkal, Shaik Rafi Ahamed:
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2149-2153 (2024) - 2023
- [j23]Thockchom Birjit Singha
Securing AES Designs Against Power Analysis Attacks: A Survey. IEEE Internet Things J. 10(16): 14332-14356 (2023) - 2022
- [j22]Satyajit Bora
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers. Circuits Syst. Signal Process. 41(2): 1131-1145 (2022) - [j21]Rohit Lorenzo
Half-selection disturbance free 8T low leakage SRAM cell. Int. J. Circuit Theory Appl. 50(5): 1557-1575 (2022) - 2021
- [j20]Satyajit Bora
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 2132-2136 (2021) - 2020
- [j19]Soham Talukder, Rajan Singh
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform. Circuits Syst. Signal Process. 39(7): 3610-3625 (2020)
2010 – 2019
- 2019
- [c22]Pralay Chakrabarty
Analysis of Electromagnetic Actuation System for Different Coil Topologies. TENCON 2019: 679-683 - [c21]Vimal Kumar Singh Yadav
Fabrication of Back to Back Schottky Micro-Diodes Using Silver Nanoparticle Film and Zinc Oxide Nanowire Mat for Biological Interactions. TENCON 2019: 1813-1817 - [c20]Rohit Lorenzo, Roy Paily:
Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue. TENCON 2019: 2549-2553 - 2017
- [j18]Saroj Mondal
On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes. IEEE Internet Things J. 4(5): 1624-1633 (2017) - [j17]Saroj Mondal
Efficient Solar Power Management System for Self-Powered IoT Node. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2359-2369 (2017) - [j16]Manchi Pavan Kumar, Roy Paily
Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard. IEEE Trans. Ind. Informatics 13(5): 2474-2483 (2017) - 2016
- [j15]Rahul Shrestha, Roy Paily
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. Circuits Syst. Signal Process. 35(8): 2832-2854 (2016) - [j14]Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. IET Circuits Devices Syst. 10(2): 111-120 (2016) - [j13]Vinaya M. M., Roy Paily
Analysis and design of moderate inversion based low power low-noise amplifier. IET Comput. Digit. Tech. 10(5): 254-260 (2016) - [j12]Saroj Mondal
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 254-258 (2016) - [c19]Vinaya M. M., Roy Paily
Power Optimization of LNA for LTE Receiver. VLSID 2016: 162-167 - [c18]Saroj Mondal
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems. VLSID 2016: 224-229 - [c17]Vaddi Chandra Sekhar, Satyajit Bora, Monalisa Dash
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms. VLSID 2016: 421-426 - [c16]Manchi Pavan Kumar, Roy Paily
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard. VLSID 2016: 581-582 - 2015
- [j11]Rahul Shrestha, Roy P. Paily
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. J. Low Power Electron. 11(3): 406-412 (2015) - [j10]Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1421-1430 (2015) - [j9]Vinaya M. M., Roy P. Paily
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2908-2919 (2015) - [j8]Rahul Shrestha, Roy P. Paily
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. J. Signal Process. Syst. 81(2): 305-320 (2015) - [c15]Vinay M. M., Roy P. Paily
A low-power subthreshold LNA for mobile applications. VDAT 2015: 1-5 - [c14]Saroj Mondal
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems. VDAT 2015: 1-5 - 2014
- [j7]Nagesh Ch, Roy P. Paily
Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application. Micromachines 5(3): 722-737 (2014) - [j6]Rahul Shrestha, Roy P. Paily
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2699-2710 (2014) - [j5]Sunil P. Joshi, Roy Paily
Distributed Arithmetic based Split-Radix FFT. J. Signal Process. Syst. 75(1): 85-92 (2014) - [c13]Rahul Shrestha, Roy Paily
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. ISED 2014: 171-175 - [c12]Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily
An efficient hardware architecture for stereo disparity estimation. VDAT 2014: 1-6 - 2013
- [j4]Rahul Shrestha, Roy P. Paily
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. IET Commun. 7(12): 1211-1220 (2013) - [c11]Rahul Shrestha, Roy P. Paily
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. ICACCI 2013: 903-907 - [c10]R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network. VDAT 2013: 26-34 - [c9]Ratul Kumar Baruah, Roy P. Paily
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance. VDAT 2013: 118-127 - [c8]Rahul Shrestha, Roy P. Paily
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. VLSI Design 2013: 86-91 - [c7]Vinay M. M., Roy Paily
Gain, NF and IIP3 Budgeting of LTE Receiver Front End. VLSI Design 2013: 191-196 - 2012
- [j3]Abdul Raouf Khalid, Roy Paily
Fpga Implementation of High Speed and Low Power Architectures for Image Segmentation using Sobel Operators. J. Circuits Syst. Comput. 21(7) (2012) - [j2]N. Ramakrishnan, Harshal B. Nemade, Roy Paily Palathinkal
Resonant Frequency Characteristics of a SAW Device Attached to Resonating Micropillars. Sensors 12(4): 3789-3797 (2012) - [c6]Rahul Shrestha, Roy P. Paily
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. VDAT 2012: 30-39 - [c5]Amrita Brahmachari, Roy P. Paily
Low power 2.4 GHz RF transmitter for satellite subsystem using CORDIC based frequency translator. WOCN 2012: 1-5 - 2011
- [j1]K. C. Narasimhamurthy, Roy P. Paily
Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes. IET Circuits Devices Syst. 5(5): 365-370 (2011) - [c4]Sudheer Kurakula, A. S. D. P. Sudhansh, Roy Paily
Design of QRS Detection and Heart Rate Estimation System on FPGA. ACC (4) 2011: 165-174 - [c3]K. C. Narasimhamurthy, Roy P. Paily
Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes. VLSI Design 2011: 208-213
2000 – 2009
- 2009
- [c2]K. C. Narasimhamurthy, Roy P. Paily
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. VLSI Design 2009: 505-510 - 2008
- [c1]Depak Balemarthy, Roy Paily
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning. ISLPED 2008: 295-300
Coauthor Index
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