default search action

combined dblp search
author search
venue search
publication search

ask others

"High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency ..."

Kumari Suravi, Rahul Shrestha (2022)

> Home

Details and statistics

DOI: 10.1109/ISVLSI54635.2022.00048

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isvlsi/SuraviS22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/SuraviS22
Kumari Suravi, Rahul Shrestha:
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems. ISVLSI 2022: 206-211

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.