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A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

Designing embedded systems efficiently has always been of significant interest. This has tremendously scaled-up for contemporary applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning (HSP) technique for the design of such systems. The Partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed.

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References

  1. Arató, P., Mann, Z.Á., Orbán, Á.: Algorithmic aspects of hardware/software partitioning. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 10(1), 136–156 (2005)

    Article  Google Scholar 

  2. Wu, J., Sun, Q., Srikanthan, T.: Algorithmic aspects for multiple-choice hardware/software partitioning. Comput. Oper. Res. 39(12), 3281–3292 (2012)

    Article  MATH  Google Scholar 

  3. Li, S.G., Feng, F.J., Hu, H.J., Wang, C., Qi, D.: Hardware/software partitioning algorithm based on genetic algorithm. J. Comput. 9(6), 1309–1315 (2014)

    Google Scholar 

  4. Jiang, Y., Zhang, H., Jiao, X., Song, X., Hung, W.N., Gu, M., Sun, J.: Uncertain model and algorithm for hardware/software partitioning. In: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 243–248. IEEE (2012)

    Google Scholar 

  5. Wu, J., Srikanthan, T., Chen, G.: Algorithmic aspects of hardware/software partitioning: 1D search algorithms. IEEE Trans. Comput. 59(4), 532–544 (2010)

    Article  MathSciNet  MATH  Google Scholar 

  6. Wang, G., Gong, W., Kastner, R.: A new approach for task level computational resource bi-partitioning. In: Fifteenth IASTED International Conference on Parallel and Distributed Computing and Systems, vol. 1, pp. 439–444. Citeseer (2003)

    Google Scholar 

  7. López-Vallejo, M., López, J.C.: On the hardware-software partitioning problem: system modeling and partitioning techniques. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 8(3), 269–297 (2003)

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. International Institute of Information Technology (IIIT) Hyderabad, Hyderabad, 500032, India

    Naman Govil

  2. School of Computing and Electrical Engineering, Indian Institute of Technology (IIT) Mandi, Mandi, 175005, Himachal Pradesh, India

    Rahul Shrestha & Shubhajit Roy Chowdhury

Authors
  1. Naman Govil
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  2. Rahul Shrestha
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  3. Shubhajit Roy Chowdhury
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Corresponding author

Correspondence to Rahul Shrestha .

Editor information

Editors and Affiliations

  1. Indian Institute of Technology Roorkee, Roorkee, India

    Brajesh Kumar Kaushik

  2. Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

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Govil, N., Shrestha, R., Roy Chowdhury, S. (2017). A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_7

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_7

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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