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Woogeun Rhee
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2020 – today
- 2024
- [j49]Liqun Feng
, Woogeun Rhee
A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter. IEEE J. Solid State Circuits 59(3): 728-739 (2024) - [j48]Bowen Wang
A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation. IEEE J. Solid State Circuits 59(6): 1656-1667 (2024) - [j47]Bo Zhou
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking. IEEE J. Solid State Circuits 59(7): 2121-2132 (2024) - [j46]Yunzhao Nie
An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 59(8): 2378-2389 (2024) - [j45]Bowen Wang
A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1590-1601 (2024) - [c79]Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang:
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS. ISSCC 2024: 266-268 - 2023
- [j44]Sanghee Lee
A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 3998-4002 (2023) - [c78]Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang:
A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector. A-SSCC 2023: 1-3 - [c77]Liqun Feng, Woogeun Rhee, Zhihua Wang:
A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter. CICC 2023: 1-2 - [c76]Yunzhao Nie, Woogeun Rhee, Zhihua Wang:
A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS. ESSCIRC 2023: 53-56 - [c75]Yunzhao Nie, Woogeun Rhee, Zhihua Wang:
A 405ps/20% Delay Range, 7.4mW/ns BPF-Based Delay Cell with ISI Mitigation for 7.5-8.5GHz IR-UWB Beamforming Receivers. ICTA 2023: 19-20 - [c74]Bowen Wang
A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation. ISSCC 2023: 460-461 - 2022
- [j43]Jung-Hwan Choi, Po-Chiun Huang
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 57(10): 2895-2897 (2022) - [j42]Meng Ni
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 481-494 (2022) - [j41]Liqun Feng
A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2448-2452 (2022) - [c73]Bowen Wang
A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection. CICC 2022: 1-2 - [c72]Bowen Wang
A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection. CICC 2022: 1-2 - [c71]Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, Woogeun Rhee, Zhihua Wang:
A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction. ICTA 2022: 74-75 - [c70]Luhua Lin, Bowen Wang
An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS. ICTA 2022: 106-107 - [c69]Su Han, Bowen Wang
An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin. ISCAS 2022: 757-760 - 2021
- [j40]Xinyu Xu, Zixiang Wan
A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3611-3620 (2021) - [j39]Jiahao Zhao
A 2.4-GHz Crystal-Less GFSK Receiver Using an Auxiliary Multiphase BBPLL for Digital Output Demodulation With Enhanced Frequency Scaling. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1143-1147 (2021) - [c68]Zixiang Wan, Xinyu Xu, Woogeun Rhee, Zhihua Wang:
A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS. ICTA 2021: 76-77 - [c67]Zixiang Wan, Woogeun Rhee
Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops. ISCAS 2021: 1-4 - 2020
- [j38]Haixin Song
A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection. IEEE J. Solid State Circuits 55(2): 219-232 (2020) - [j37]Xuqiang Zheng
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits 55(6): 1651-1664 (2020) - [c66]Haixin Song, Woogeun Rhee
A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity. CICC 2020: 1-4 - [c65]Zixiang Wan, Woogeun Rhee
A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation. ICTA 2020: 19-20 - [c64]Xinyu Xu, Woogeun Rhee, Zhihua Wang:
A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation. ISCAS 2020: 1-4 - [c63]Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee
A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. MWSCAS 2020: 341-344 - [c62]Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee
A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. MWSCAS 2020: 345-348 - [c61]Xiaohua Huang, Bowen Wang
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [j36]Yining Zhang
A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation. IEEE J. Solid State Circuits 54(2): 336-345 (2019) - [j35]Yining Zhang
A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 36-40 (2019) - [c60]Cong Ding
A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL. A-SSCC 2019: 291-294 - [c59]Xiaohua Huang
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. CICC 2019: 1-4 - [c58]Cong Ding
A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1+-Point Modulation. ISCAS 2019: 1-4 - [c57]Xiaohua Huang, Kunnong Zeng, Woogeun Rhee
A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering. ISCAS 2019: 1-4 - [c56]Yuguang Liu, Haixin Song, Kunnong Zeng, Woogeun Rhee
A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity. VLSI-DAT 2019: 1-4 - [c55]Yining Zhang, Jiahao Zhao, Woogeun Rhee
Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation. VLSI-DAT 2019: 1-4 - 2018
- [j34]Jianfu Lin
A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector. IEEE J. Solid State Circuits 53(10): 2850-2863 (2018) - [j33]Fei Chen
A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 196-200 (2018) - [j32]Zhaoyang Weng, Hanjun Jiang
400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 745-757 (2018) - [j31]Xiaohua Huang
A 1-GHz 1.6-mW Auto-Calibrated Bit Slicer for Energy/Envelope Detection Receivers. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 587-591 (2018) - [j30]Yanshu Guo, Hanjun Jiang
A 120 pJ/bit ΔΣ-Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1854-1858 (2018) - [c54]Haixin Song, Dang Liu, Woogeun Rhee
A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands. A-SSCC 2018: 295-298 - [c53]Dang Liu, Xiaohua Huang, Zhendong Ding, Haixin Song, Woogeun Rhee
A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications. CICC 2018: 1-4 - [c52]Xiaohua Huang, Han Liu, Woogeun Rhee
A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems. VLSI-DAT 2018: 1-4 - 2017
- [j29]Dang Liu
A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications. IEEE J. Solid State Circuits 52(6): 1479-1494 (2017) - [j28]Yining Zhang
A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL. IEEE J. Solid State Circuits 52(10): 2627-2635 (2017) - [j27]Xican Chen
A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 969-980 (2017) - [c51]Jianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee
A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector. A-SSCC 2017: 317-320 - [c50]Woogeun Rhee
Session 15 - Energy-efficient wireless for 5G and IoT. CICC 2017: 1 - [c49]Yining Zhang, Ranran Zhou
A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies. CICC 2017: 1-4 - [c48]Yudong Zhang, Xiaofeng Liu, Woogeun Rhee
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. ISCAS 2017: 1-4 - [c47]Ranran Zhou
An energy/bandwidth/area efficient frequency-domain OOK transmitter with phase rotated modulation. ISCAS 2017: 1-4 - 2016
- [c46]Yining Zhang, Ranran Zhou
A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL. A-SSCC 2016: 277-280 - [c45]Woogeun Rhee, Eric A. M. Klumperink, Hossein Hashemi:
EE4: Eureka! The best moments of solid-state circuit design in the 2000s. ISSCC 2016: 521 - [c44]Woogeun Rhee
An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation. MWSCAS 2016: 1-4 - 2015
- [j26]Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee
A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications. IEEE J. Solid State Circuits 50(3): 669-678 (2015) - [j25]Yudong Zhang, Woogeun Rhee
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 736-740 (2015) - [c43]Chao Yang, Shaoquan Gao, Jingjing Dong, Hanjun Jiang, Woogeun Rhee
A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications. ASICON 2015: 1-4 - [c42]Dang Liu, Xiaofeng Liu, Woogeun Rhee
A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications. A-SSCC 2015: 1-4 - [c41]Ni Xu, Yiyu Shen, Sitao Lv, Woogeun Rhee
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation. A-SSCC 2015: 1-4 - [c40]Woogeun Rhee
Phase-locked frequency synthesis and modulation for modern wireless transceivers. CICC 2015: 1-75 - [c39]Yiyu Shen, Woogeun Rhee
A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters. ISCAS 2015: 662-665 - [c38]Xiaoyong Li, Woogeun Rhee
A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path. ISCAS 2015: 894-897 - [c37]Heng Liu, Hanjun Jiang, Yiyu Shen, Woogeun Rhee
A delta-sigma-based transmitter utilizing FIR-embedded digital power amplifiers. MWSCAS 2015: 1-4 - [c36]Yanfeng Li, Yutao Liu, Woogeun Rhee
A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator. VLSI-DAT 2015: 1-4 - 2014
- [j24]Ni Xu, Woogeun Rhee
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation. IEEE J. Solid State Circuits 49(10): 2172-2186 (2014) - [j23]Yutao Liu, Yizhi Han, Woogeun Rhee
A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 680-688 (2014) - [j22]Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 209-213 (2014) - [j21]Xican Chen, Wei Zhang, Woogeun Rhee
A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 932-936 (2014) - [c35]Yang Li, Ni Xu, Yining Zhang, Woogeun Rhee
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications. A-SSCC 2014: 261-264 - [c34]Xiaowei Han, Beibei Wang, An Wang, Liji Wu, Woogeun Rhee
Algorithm-Based Countermeasures against Power Analysis Attacks for Public-Key Cryptography SM2. CIS 2014: 435-439 - [c33]Yanfeng Li, Ni Xu, Woogeun Rhee
A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL. ISCAS 2014: 1440-1443 - [c32]Dang Liu, Shuli Geng, Woogeun Rhee
A high efficiency robust IR-UWB receiver design for high data rate CM-range communications. ISCAS 2014: 1901-1904 - [c31]Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee
9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications. ISSCC 2014: 160-161 - [c30]Fei Chen, Yu Li, Dang Liu, Woogeun Rhee
9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability. ISSCC 2014: 162-163 - [c29]Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux:
F5: Low-power radios for sensor networks. ISSCC 2014: 518-519 - [c28]Wei Zhang, Yizhi Han, Fei Chen, Bo Zhou, Xican Chen, Woogeun Rhee
A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC. VLSI-DAT 2014: 1-4 - [c27]Huiying Zhuo, Yu Li, Woogeun Rhee
A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS. VLSI-DAT 2014: 1-4 - 2013
- [j20]Chang-Hyun Kim, Hong June Park, Woogeun Rhee
Introduction to the Special Section on the 2012 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 48(11): 2579-2581 (2013) - [j19]Wei Zhang, Xican Chen, Fei Chen, Woogeun Rhee
A Phase-Domain ΔΣ Ranging Method for FMCW Radar Receivers. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 537-541 (2013) - [j18]Bo Zhou, Woogeun Rhee
Reconfigurable FM-UWB transmitter design for robust short range communications. Telecommun. Syst. 52(2): 1133-1144 (2013) - [c26]Fei Chen, Yu Li, Deyuan Lin, Huiying Zhuo, Woogeun Rhee
A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation. CICC 2013: 1-4 - [c25]Shuli Geng, Ni Xu, Jun Li, Xueyi Yu, Woogeun Rhee
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation. ISCAS 2013: 1179-1182 - [c24]Dang Liu, Fei Chen, Woogeun Rhee
An FM-UWB transceiver with M-PSK subcarrier modulation and regenerative FM demodulation. MWSCAS 2013: 936-939 - [c23]Hang Lv, Bo Zhou, Dang Liu, Woogeun Rhee
A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems. VLSI-DAT 2013: 1-4 - 2012
- [j17]Woogeun Rhee
Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. 2012: 941653:1-941653:2 (2012) - [j16]Shen-Iuan Liu, Tsung-Hsien Lin
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 47(11): 2551-2553 (2012) - [j15]Bo Zhou, Jian Qiao, Rui He, Jinghui Liu, Wei Zhang, Hang Lv, Woogeun Rhee
A Gated FM-UWB System With Data-Driven Front-End Power Control. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1348-1358 (2012) - [j14]Nan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Ni Xu, Patrick Chiang, Woogeun Rhee
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1720-1732 (2012) - [c22]Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ISCAS 2012: 313-316 - [c21]Wei Zhang, Woogeun Rhee
A ΔΣ IR-UWB radar with sub-mm ranging capability for human body monitoring systems. ISCAS 2012: 1315-1318 - [c20]Shuli Geng, Woogeun Rhee
A pulse-shaped power amplifier with dynamic bias switching for IR-UWB transmitters. ISCAS 2012: 2529-2532 - [c19]Ranjit Gharpurey, Woogeun Rhee:
Session 26 overview: Short-range wireless transceivers: Wireless subcommittee. ISSCC 2012: 438-439 - [c18]Yizhi Han, Woogeun Rhee
A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL. MWSCAS 2012: 542-545 - 2011
- [j13]Ni Xu, Woogeun Rhee
Semidigital PLL Design for Low-Cost Low-Power Clock Generation. J. Electr. Comput. Eng. 2011: 235843:1-235843:9 (2011) - [j12]Yuanfeng Sun, Jian Qiao, Xueyi Yu, Woogeun Rhee
A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2149-2158 (2011) - [c17]Zhuo Zhang, Woogeun Rhee
A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid. ISCAS 2011: 474-477 - [c16]Hang Lv, Bo Zhou, Woogeun Rhee
A relaxation oscillator with multi-phase triangular waveform generation. ISCAS 2011: 2837-2840 - 2010
- [c15]Yutao Liu, Ni Xu, Woogeun Rhee
Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit. APCCAS 2010: 939-942 - [c14]Jun Li, Ni Xu, Yuanfeng Sun, Woogeun Rhee
Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis. APCCAS 2010: 1135-1138 - [c13]Woogeun Rhee
Low power, non invasive UWB systems for WBAN and biomedical applications. ICTC 2010: 35-40
2000 – 2009
- 2009
- [j11]Xueyi Yu, Yuanfeng Sun, Woogeun Rhee
A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. IEEE J. Solid State Circuits 44(8): 2193-2201 (2009) - [j10]Xueyi Yu, Yuanfeng Sun, Woogeun Rhee
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators. IEEE J. Solid State Circuits 44(9): 2426-2436 (2009) - [j9]Li Zhang, Xueyi Yu, Yuanfeng Sun, Woogeun Rhee
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops. IEEE J. Solid State Circuits 44(11): 2922-2934 (2009) - [c12]Rui He, Jun Li, Woogeun Rhee
Transient Analysis of Nonlinear Settling Behavior in Charge-pump Phase-locked Loop Design. ISCAS 2009: 469-472 - [c11]Jian Qiao, Xueyi Yu, Woogeun Rhee
Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL. ISCAS 2009: 2401-2404 - [c10]Xueyi Yu, Woogeun Rhee
A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation. ISSCC 2009: 398-399 - 2008
- [j8]Woogeun Rhee
Experimental Analysis of Substrate Noise Effect on PLL Performance. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 638-642 (2008) - [c9]Xueyi Yu, Yuanfeng Sun, Woogeun Rhee
A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications. CICC 2008: 753-756 - [c8]Xueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering. ISSCC 2008: 346-347 - 2007
- [j7]Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. IEEE J. Solid State Circuits 42(8): 1635-1641 (2007) - [c7]Baoyong Chi, Xueyi Yu, Woogeun Rhee
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. ISCAS 2007: 3051-3054 - [c6]Yong Liu, Woogeun Rhee
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. ISSCC 2007: 176-595 - 2006
- [j6]John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41(12): 2885-2900 (2006) - [c5]Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. CICC 2006: 671-674 - [c4]Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC 2006: 213-222 - 2005
- [j5]Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. IEEE J. Solid State Circuits 40(12): 2633-2645 (2005) - 2004
- [j4]Woogeun Rhee
A semi-digital delay-locked loop using an analog-based finite state machine. IEEE Trans. Circuits Syst. II Express Briefs 51-II(11): 635-639 (2004) - 2003
- [c3]Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer:
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC 2003: 81-84 - 2002
- [j3]Woogeun Rhee
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution. IEEE J. Solid State Circuits 37(4): 515-520 (2002) - [j2]Rahul Magoon, Alyosha C. Molnar, Jeff Zachan, Geoff Hatcher, Woogeun Rhee
A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer. IEEE J. Solid State Circuits 37(12): 1710-1720 (2002) - 2001
- [b1]Woogeun Rhee:
Multi-Bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers. University of Illinois Urbana-Champaign, USA, 2001 - 2000
- [j1]Woogeun Rhee
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator. IEEE J. Solid State Circuits 35(10): 1453-1460 (2000)
1990 – 1999
- 1999
- [c2]Woogeun Rhee, Akbar Ali:
An on-chip phase compensation technique in fractional-N frequency synthesis. ISCAS (3) 1999: 363-366 - [c1]Woogeun Rhee:
Design of low-jitter 1-GHz phase-locked loops for digital clock generation. ISCAS (2) 1999: 520-523
Coauthor Index
[j49] [j48] [j47] [j46] [j45] [c79] [c78] [c77] [c76] [c75] [c74] [j42] [j41] [c73] [c72] [c71] [c70] [c69] [j40] [j39] [c68] [c67] [j38] [c66] [c65] [c64] [c63] [c62] [c61] [j36] [j35] [c60] [c59] [c58] [c57] [c56] [c55] [j34] [j33] [j32] [j31] [j30] [c54] [c53] [c52] [j29] [j28] [j27] [c49] [c48] [c47] [c46] [c44] [j26] [j25] [c43] [c42] [c41] [c39] [c38] [c37] [c36] [j24] [j23] [j21] [c35] [c33] [c32] [c31] [c30] [c28] [c27] [j19] [j18] [c26] [c25] [c24] [c23] [j15] [j14] [c22] [c21] [c20] [c18] [j13] [j12] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [j9] [c12] [c11] [c10] [c9] [c8] [c7]
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