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Mounir Meghelli
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2020 – today
- 2024
- [c26]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli:
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC 2024: 1-8 - [c25]Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli:
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j25]Timothy O. Dickson
, Zeynep Toprak Deniz
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - 2022
- [c24]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c23]Serdar S. Yonar, Pier Andrea Francese
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - 2020
- [j24]Zeynep Toprak Deniz
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55(1): 19-26 (2020) - [j23]Zeynep Toprak Deniz
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55(4): 1124 (2020)
2010 – 2019
- 2019
- [c22]Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC 2019: 122-124 - [c21]Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski:
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC 2019: 1-3 - [c20]Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt:
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. OFC 2019: 1-3 - 2018
- [j22]Jonathan E. Proesel
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(4): 1214-1226 (2018) - [j21]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [c19]Mounir Meghelli, Hyeon-Min Bae, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. ISSCC 2018: 100-101 - [c18]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC 2018: 266-268 - [c17]Bo Zhang, Frederic Gianesello, Simone Erba, Mounir Meghelli, Azita Emami, Takayuki Shibasaki:
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. ISSCC 2018: 514-516 - [c16]Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green:
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. OFC 2018: 1-3 - 2017
- [j20]Tim Piessens
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 52(12): 3115-3118 (2017) - [j19]Ilter Özkaya
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [c15]Rahel Strässle, Sebastian Gerke, Thomas Brunschwiler, Yuksel Temiz, Jonas R. M. Weiss, Arvind Sridhar, Stephan Paredes, Emanuel Loertscher, Neil Ebejer, Bruno Michel, H.-M. Lee, C. Alvarado, Ismael Faro, T. van Kessel, Mounir Meghelli, Marc A. Taubenblatt, Sufi Zafar, Frank Libsch, Keiji Matsumoto:
Internet of the Body and Cognitive Hypervisor. CHASE 2017: 296-297 - [c14]Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli:
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. ISSCC 2017: 118-119 - [c13]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - 2016
- [j18]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman:
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51(8): 1744-1755 (2016) - [c12]Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli:
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC 2016: 56-57 - [c11]Jason S. Orcutt, Douglas M. Gill, Jonathan E. Proesel, John J. Ellis-Monaghan, Folkert Horst, Tymon Barwicz, Chi Xiong, Frederick G. Anderson, Ankur Agrawal, Yves Martin, Christian W. Baks, Marwan Khater, Jessie C. Rosenberg, W. D. Sacher, Jens Hofrichter, Edward Kiewra, Andreas D. Stricker, Frank Libsch, Bert Jan Offrein, Mounir Meghelli, Natalie B. Feilchenfeld, Wilfried Haensch, William M. J. Green:
Monolithic silicon photonics at 25 Gb/s. OFC 2016: 1-3 - 2015
- [j17]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. IEEE J. Solid State Circuits 50(12): 3120-3132 (2015) - [c10]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman:
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC 2015: 1-4 - [c9]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli:
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. ISSCC 2015: 1-3 - [c8]Benjamin G. Lee, Renato Rimolo-Donadio, Alexander V. Rylyakov, Jonathan E. Proesel, John F. Bulzacchelli, Christian W. Baks, Mounir Meghelli, Clint L. Schow, Anand Ramaswamy, Jonathan E. Roth, Jae-Hyuk Shin, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish:
A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. OFC 2015: 1-3 - [c7]Anand Ramaswamy, Jonathan E. Roth, Erik J. Norberg, Robert S. Guzzon, Jae-Hyuk Shin, J. T. Imamura, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish, Benjamin G. Lee, Renato Rimolo-Donadio, Christian W. Baks, Alexander V. Rylyakov, Jonathan E. Proesel, Mounir Meghelli, Clint L. Schow:
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. OFC 2015: 1-3 - [c6]Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Clint Schow, Mounir Meghelli:
A 25 Gb/s burst-mode receiver for low latency photonic switch networks. OFC 2015: 1-3 - 2014
- [j16]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 49(11): 2474-2489 (2014) - 2013
- [c5]Glenn E. R. Cowan, Mounir Meghelli, Daniel J. Friedman:
A linearized voltage-controlled oscillator for dual-path phase-locked loops. ISCAS 2013: 2678-2681 - 2012
- [j15]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(8): 1828-1841 (2012) - 2011
- [c4]Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli:
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology. CICC 2011: 1-4
2000 – 2009
- 2008
- [j14]Mounir Meghelli, Robert Shimon:
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08). IEEE J. Solid State Circuits 43(10): 2175-2176 (2008) - 2006
- [j13]James F. Buckwalter, Mounir Meghelli, Daniel J. Friedman, Ali Hajimiri
Phase and amplitude pre-emphasis techniques for low-power serial links. IEEE J. Solid State Circuits 41(6): 1391-1399 (2006) - [j12]John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41(12): 2885-2900 (2006) - [c3]Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC 2006: 213-222 - 2005
- [j11]Mounir Meghelli:
A 43-Gb/s full-rate clock transmitter in 0.18-μm SiGe BiCMOS technology. IEEE J. Solid State Circuits 40(10): 2046-2050 (2005) - [j10]Behnam Analui, Alexander V. Rylyakov, Sergey V. Rylov
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. IEEE J. Solid State Circuits 40(12): 2689-2699 (2005) - 2004
- [j9]Mounir Meghelli:
132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology. IEEE J. Solid State Circuits 39(12): 2403-2407 (2004) - 2003
- [j8]Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer:
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47(2-3): 259-282 (2003) - [j7]Mounir Meghelli, Alexander V. Rylyakov, Steven Zier, Michael Sorna, Daniel J. Friedman:
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE J. Solid State Circuits 38(12): 2147-2154 (2003) - [c2]Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman:
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. CICC 2003: 313-316 - 2002
- [j6]Greg G. Freeman, Mounir Meghelli, Young Kwark, Steven Zier, Alexander V. Rylyakov, Michael Sorna, Todd Tanji, Oswin M. Schreiber, Keith Walter, Jae-Sung Rieh, Basanth Jagannathan, Alvin J. Joseph, Seshadri Subbanna:
40-Gb/s circuits built from a 120-GHz fT SiGe technology. IEEE J. Solid State Circuits 37(9): 1106-1114 (2002) - [j5]Mounir Meghelli, Alexander V. Rylyakov, Lei Shan:
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. IEEE J. Solid State Circuits 37(12): 1790-1794 (2002) - 2000
- [j4]Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer:
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. IEEE J. Solid State Circuits 35(12): 1992-1995 (2000) - [j3]Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart:
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88(10): 1572-1582 (2000)
1990 – 1999
- 1998
- [j2]Philippe André, Jean-Louis Benchimol, Patrick Desrousseaux, Anne-Marie Duchenois, Jean Godin, Agnieszka Konczykowska, Mounir Meghelli, Muriel Riet, André Scavennec:
InP DHBT technology and design methodology for high-bit-rate optical communications circuits. IEEE J. Solid State Circuits 33(9): 1328-1335 (1998) - [j1]Mounir Meghelli, Michel Bouché, Agnieszka Konczykowska:
High power and high speed InP DHBT driver IC's for laser modulation. IEEE J. Solid State Circuits 33(9): 1411-1416 (1998) - [c1]Agnieszka Konczykowska, Mounir Meghelli:
Very high speed integrated circuits for optical communication. ICECS 1998: 189-192
Coauthor Index
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last updated on 2024-10-18 20:28 CEST by the dblp team
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