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IET Computers & Digital Techniques, Volume 10
Volume 10, Number 1, January 2016
- Shervin Vakili
, J. M. Pierre Langlois, Guy Bois:
Accuracy-aware processor customisation for fixed-point arithmetic. 1-11 - Irith Pomeranz:
Static test compaction for circuits with multiple independent scan chains. 12-17 - Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi
Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m ). 18-29 - Aiman H. El-Maleh
Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits. 30-36 - Hanmin Park, Kiyoung Choi:
Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip. 37-44
Volume 10, Number 2, March 2016
- Irith Pomeranz:
Improving the accuracy of defect diagnosis by adding and removing tests. 47-53 - Cheeckottu Vayalil Niras, Yinan Kong:
Fast sign-detection algorithm for residue number system moduli set {2 n - 1, 2 n , 2 n+1 - 1}. 54-58 - Nithish Kumar Venkatachalam
Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios. 59-68 - Sa'ed Abed
Hybrid approach based on partial tag comparison technique and search methods to improve cache performance. 69-76 - Simone Libutti, Giuseppe Massari
Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective. 77-84 - Charalampos Chalios
Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics. 85-92
Volume 10, Number 3, May 2016
- Swaminathan Kathirvel
Design of a novel energy efficient topology for maximum magnitude generator. 93-101 - Miguel Morales-Sandoval
Scalable GF(p) Montgomery multiplier based on a digit-digit computation approach. 102-109 - Debasri Saha, Susmita Sur-Kolay:
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip. 110-118 - Nilina Bera, Subhashis Majumder, Bhargab B. Bhattacharya:
Simulation-based method for optimum microfluidic sample dilution using weighted mix-split of droplets. 119-127 - Chaohui Wang, Weiguo Wu, Shiqiang Nie, Depei Qian:
BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system. 128-137 - Irith Pomeranz:
Combined input test data volume reduction for mixed broadside and skewed-load test sets. 138-145
Volume 10, Number 4, July 2016
- Liu Han, Hao Zhang
Decimal floating-point fused multiply-add with redundant internal encodings. 147-156 - Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran
Switchable cache: utilising dark silicon for application specific cache optimisations. 157-164 - Sima Afsharpour, Ahmad Patooghy
Performance/energy aware task migration algorithm for many-core chips. 165-173 - Qutaiba Ibrahim
Enhanced power management scheme for embedded road side units. 174-185 - Viacheslav Borisovich Marakhovsky, Alexey Vadimovich Surkov:
Globally asynchronous systems of interactive Moore state machines. 186-192 - Liang Geng, Jizhong Shen, Congyuan Xu:
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. 193-201
Volume 10, Number 5, September 2016
- Mark Zwolinski
Guest Editorial. 203-204 - Arindam Banerjee
A New Squarer design with reduced area and delay. 205-214 - Govinda Rao Locharla
Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT. 215-225 - Niyati Gupta, Ashish Sharma, Vijay Laxmi
σ n LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip. 226-232 - Sarit Chakraborty, Susanta Chakraborty, Chandan Das, Parthasarathi Dasgupta:
Efficient two phase heuristic routing technique for digital microfluidic biochip. 233-242 - Debasis Dhal, Piyali Datta, Arpan Chakraborty, Goutam Saha
Multiple parallel assay operations with cross contamination avoidance in a given biochip. 243-253 - Vinaya M. M., Roy Paily
Analysis and design of moderate inversion based low power low-noise amplifier. 254-260 - Vinayak Pachkawade
Mechanically coupled ring-resonator filter and array (analytical and finite element model). 261-267 - Rekha Chaudhary, Amit Sharma
Fabrication and characterisation of Al gate n-metal-oxide-semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor. 268-272 - Debarati Dey, Pradipta Roy, Debashis De
Electronic characterisation of atomistic modelling based electrically doped nano bio p-i-n FET. 273-285
Volume 10, Number 6, November 2016
- Andy M. Tyrrell:
Guest Editorial. 287 - Aviral Shrivastava
Automatic management of Software Programmable Memories in Many-core Architectures. 288-298 - Steve B. Furber
Brain-inspired computing. 299-305 - Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza:
Inexact-aware architecture design for ultra-low power bio-signal analysis. 306-314 - Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric:
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. 315-322
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