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Congyuan Xu
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2020 – today
- 2024
- [j10]Gang Ke, Shi Wang, Jun Yang, Xiaoyun Xia, Congyuan Xu, Feng Liu:
Design and Implementation of Automatic Punching Management System Based on Computer Vision. J. Inf. Sci. Eng. 40(3): 551-566 (2024) - 2021
- [j9]Congyuan Xu, Jizhong Shen, Xin Du:
Low-rate DoS attack detection method based on hybrid deep neural networks. J. Inf. Secur. Appl. 60: 102879 (2021) - 2020
- [j8]Congyuan Xu, Jizhong Shen, Xin Du:
A Method of Few-Shot Network Intrusion Detection Based on Meta-Learning Framework. IEEE Trans. Inf. Forensics Secur. 15: 3540-3552 (2020)
2010 – 2019
- 2019
- [j7]Congyuan Xu, Jizhong Shen, Xin Du:
Detection method of domain names generated by DGAs based on semantic representation and deep neural network. Comput. Secur. 85: 77-88 (2019) - 2018
- [j6]Congyuan Xu, Jizhong Shen, Xin Du, Fan Zhang:
An Intrusion Detection System Using a Deep Neural Network With Gated Recurrent Units. IEEE Access 6: 48697-48707 (2018) - [c1]Fan Zhang, Yiran Zhang, Shengwen Shi, Shize Guo, Ziyuan Liang, Samiya Qureshi, Congyuan Xu:
Optimized Lightweight Hardware Trojan-Based Fault Attack on DES. ICPADS 2018: 654-661 - 2017
- [j5]Maoqun Yao, Kai Yang, Jizhong Shen, Congyuan Xu:
Function synthesis algorithm based on RTD-based three-variable universal logic gates. Frontiers Inf. Technol. Electron. Eng. 18(10): 1654-1664 (2017) - 2016
- [j4]Liang Geng, Jizhong Shen, Congyuan Xu:
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. IET Comput. Digit. Tech. 10(4): 193-201 (2016) - [j3]Liang Geng, Jizhong Shen, Congyuan Xu:
Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme. Frontiers Inf. Technol. Electron. Eng. 17(9): 962-972 (2016) - 2015
- [j2]Maoqun Yao, Kai Yang, Congyuan Xu, Jizhong Shen:
Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate. J. Appl. Math. 2015: 827572:1-827572:7 (2015) - [j1]Maoqun Yao, Kai Yang, Congyuan Xu, Jizhong Shen:
Design of a novel RTD-based three-variable universal logic gate. Frontiers Inf. Technol. Electron. Eng. 16(8): 694-699 (2015)
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last updated on 2024-10-08 21:29 CEST by the dblp team
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