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SoCC 2010: Las Vegas, NV, USA
- Thomas Büchner, Ramalingam Sridhar, Andrew Marshall, Norbert Schuhmann:
Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings. IEEE 2010, ISBN 978-1-4244-6682-5
SoC Power Optimization Techniques
- Rashmi Mehrotra, Tom English, Emanuel M. Popovici, Michel P. Schellekens:
Delay dependent power optimisation of combinational circuits using AND-Inverter graphs. 9-14 - Selçuk Köse
, Eby G. Friedman:
Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors. 15-18 - Na Gong, Ramalingam Sridhar:
Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation. 19-24 - Imen Mansouri, Fabien Clermidy, Pascal Benoit, Lionel Torres:
A run-time distributed cooperative approach to optimize power consumption in MPSoCs. 25-30
Analog 1
- Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis:
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks. 33-38 - Minah Kwon, Dahsom Kim, Daeyun Kim, Junho Moon, Minkyu Song:
A digitally self-calibrated low-noise 7-bit folding A/D converter. 39-43 - Jong-Kwan Woo, Hyunjoong Lee, SungHo Ahn, Suhwan Kim:
A high-resolution and fast-conversion readout circuit for differential capacitive sensors. 44-47 - Hongjiang Song, Jianan Song, Aritra Dey, Yan Song:
Jitter transfer function model and VLSI jitter filter circuits. 48-51
Embedded Tutorial
- Thomas Büchner:
A holistic view on low power design. 55
Low Power SoC Circuits
- Gang Chen, Yifei Luo, Jiayin Tian, Kuan Zhou:
A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step. 59-64 - Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham:
High speed recursion-free CORDIC architecture. 65-70 - Ralph Oberhuber, Rahul Prakash, Vadim Ivanov:
A 1 ppm/°C bandgap voltage reference with new second-order Taylor curvature compensation. 71-76
Analog 2
- Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung:
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster. 79-82 - Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS. 84-87 - Jae-Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang:
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. 88-91
Embedded Tutorial
- Kaijian Shi:
Low-power SOC implementation: What you need to know. 95
Multimedia Processing
- Ning Ma, Zhonghai Lu, Zhibo Pang, Li-Rong Zheng:
System-level exploration of mesh-based NoC architectures for multimedia applications. 99-104 - Soonwoo Choi, Jason Jong Kyu Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae:
A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor. 105-108 - Xin Zhao, Ying Yi, Ahmet T. Erdogan
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras. 109-112 - Markus Holzer, Ruben Bartholomä, Thomas Greiner, Wolfgang Rosenstiel:
Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations. 113-118
System Level Design Methodologies
- Won Ha Choi, Xun Liu:
Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming. 121-126 - Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Unleash the parallelism of 3DIC partitioning on GPGPU. 127-132 - Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen:
Routability-driven RDL routing with pin reassignment. 133-138 - Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, Yu-Min Lee:
Statistical electro-thermal analysis with high compatibility of leakage power models. 139-144
Design
- Hiroki Sunagawa, Hidetoshi Onodera:
Variation-tolerant design of D-flipflops. 147-151 - Young Bok Kim, Yong-Bin Kim:
High speed and low power transceiver design with CNFET and CNT bundle interconnect. 152-157 - Sangwoo Han, Juho Kim:
NBTI-aware statistical timing analysis framework. 158-163 - Chiu-Kuo Chen, Ericson Chua, Shao-Yen Tseng, Chih-Chung Fu, Wai-Chi Fang:
Implementation of a hardware-efficient EEG processor for brain monitoring systems. 164-168 - Ye Lu, Sakir Sezer, John V. McCanny:
Design and analysis of an advanced static blocked multithreading architecture. 169-173
System Level Design Methodologies
- Siwat Saibua, Po-Yu Kuo, Dian Zhou, Ming-e Jing:
A Folding Strategy for SAT solvers based on Shannon's expansion theorem. 177-181 - Dan Liu, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang:
TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures. 182-187 - Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang
Expandable MDC-based FFT architecture and its generator for high-performance applications. 188-192 - Thomas Uhle, Karsten Einwich:
A SystemCAMS extension for the simulation of non-linear circuits. 193-198 - Moazzam Fareed Niazi, Tiberiu Seceleanu
An automated control code generation approach for the SegBus platform. 199-204
Luncheon
- P. R. Mukund:
From Film to Silicon: The Migration of Document Archiving Technology. 205
Low Power Design
- Tien-Hung Lin, Po-Tsang Huang, Wei Hwang:
Power noise suppression technique using active decoupling capacitor for TSV 3D integration. 209-212 - Tung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham:
Estimation of maximum application-level power supply noise. 213-218 - Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen:
Simultaneous voltage island generation and floorplanning. 219-223 - Rahul Singh, AhReum Kim, Suhwan Kim:
Footer voltage feedforward domino technique for wide fan-in dynamic logic. 224-229 - Ankitchandra Shah, Hamid Mahmoodi
Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits. 230-235 - Yu-Jen Huang, Yun-Chao You, Jin-Fu Li:
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. 236-240
Reconfigurable Systems
- Yuji Aoyama, Minoru Watanabe:
Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array. 243-247 - Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. 248-253 - Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hongying Meng
Binary object recognition system on FPGA with bSOM. 254-259 - Naifeng Jing, Weifeng He, Zhigang Mao:
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. 260-265 - Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija:
Design of a link-controller architecture for multiple serial link protocols. 266-271 - Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
High-Performance random data lookup for network processing. 272-277
Poster Session
Analog and Mixed Signals
- Jiaping Hu, Yong-Bin Kim, Joseph Ayers
A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. 281-284 - HeungJun Jeon, Yong-Bin Kim:
A CMOS low-power low-offset and high-speed fully dynamic latched comparator. 285-288 - Kwang Yoon, Won Kim:
A CMOS 6 bit 250MS/s A/D converter with input voltage range detectors. 289-292 - Shao-Ku Kao, Yong-De You:
Clock buffer with duty cycle corrector. 293-296 - Xiong Liu, Alan N. Willson Jr.:
A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOS. 297-300 - Mohammed Younus, Hongjiang Song:
8Gbps high-speed I/O transmitter with scalable speed, swing and equalization levels. 301-304
Reconfigurable and Programmable Circuits and Systems, FPGAs
- Binbin Wu, Like Yan, Yuan Wen, Tianzhou Chen:
Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration. 305-308 - Mohammed A. S. Abdallah, Omar S. Elkeelany
A multi-channel frequency detection and monitoring system. 309-312
Embedded Systems, Multi Core, and Embedded Memory
- Gururaj Shamanna, Bhunesh S. Kshatri, Raja Gaurav, Y. S. Tew, Percy Marfatia, Y. K. Raghavendra, V. Naik:
Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness. 313-316 - Jiangjiang Liu, Jianyong Zhang, Nihar R. Mahapatra:
Interconnect system compression analysis for multi-core architectures. 317-320
Low Power
- Jinhui Wang, Na Gong, Wuchen Wu, Ligang Hou:
Fan-in sensitive low power dynamic circuits performance statistical characterization. 321-325 - Senthil Jayapal, Jan Stuijt, Jos Huisken
Energy efficient computation with self-adaptive single-ended body bias. 326-329 - Osman Kubilay Ekekon, Samed Maltabas, Martin Margala
Power minimization methodology for VCTL topologies. 330-333 - Kyung Ki Kim, Haiqing Nan, Ken Choi:
Hybrid MOSFET/CNFET based power gating structure. 334-338
Verification
- Anuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi
Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies. 339-342 - Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya:
A BDD-based approach to design power-aware on-line detectors for digital circuits. 343-346 - Weifeng He, Weiwei Chen, Zhigang Mao:
An efficient VLSI architecture for extended variable block sizes motion estimation. 347-350
Multimedia Processing
- Tuyet-Trang Lam, Ricardo Citro:
A multimedia content generation methodology in support to SOC decoder development and validation. 351-354 - Paul V. Jansz-Drávetzky, Steven Hinckley, Graham Wild:
Effect of a polywell leometry on a CMOS photodiode array. 355-358
Network on Chip and Interconnect
- Fangfa Fu, Siyue Sun, Xin'an Hu, Junjie Song, Jinxiang Wang, Mingyan Yu:
MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoC. 359-362 - Rana Farah, Haidar Harmanani
A method for efficient NoC test scheduling using deterministic routing. 363-366 - Everton Carara, Fernando Moraes
Flow oriented routing for NOCS. 367-370 - Marek S. Tudruj
A globally-interconnected modular CMP system with communication on the fly. 371-374 - Yiou Chen, Jianhao Hu, Gengsheng Chen, Xiang Ling:
Energy and delay-aware mapping for real-time digital processing system on network on chip platforms. 375-378 - Kameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila
Thermal modelling of 3D multicore systems in a flip-chip package. 379-383 - Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu:
Efficient multicasting scheme for irregular mesh-based NoCs. 384-387
System Level Design Methodology
- Johannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner:
Towards formal system-level verification of security requirements during hardware/software codesign. 388-391 - Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen:
Thermal via planning for temperature reduction in 3D ICs. 392-395 - SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
A design procedure of predictive RF MOSFET model for compatibility with ITRS. 396-399
Plenary Session
- Jo Dale Carothers:
What You Need to Know About Patent Litigation. 403 - Siegfried Brandstätter, Burkhard Neurauter, Mario Huemer:
A novel architectural approach for control architectures in RF transceivers. 407-412 - Qin Zhou, Jia Mao, Zhuo Zou, Fredrik Jonsson, Li-Rong Zheng:
A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receivers. 413-416 - Qihang Shi, Xinzhi Xu, Jingbo Guo:
A novel architecture for discrete chaotic signal generators. 417-422
Embedded Tutorial
- Lech Józwiak:
Quality-driven SoC architecture synthesis for embedded applications. 425-426
Network on Chip 1
- Wen-Chung Tsai, Ying-Cherng Lan, Sao-Jie Chen
DyML: Dynamic Multi-Level flow control for Networks on Chip. 429-434 - Jon Nafziger, Annie Avakian, Ranga Vemuri
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. 435-440 - Chaochao Feng, Zhonghai Lu, Axel Jantsch
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. 441-446 - Ankit More, Baris Taskin:
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC. 447-452
Embedded Memory and Systems 1
- Bai Na, Xuan Chen, Yang Jun, Longxin Shi:
A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme. 455-460 - Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. 461-466 - Xiaowen Chen, Zhonghai Lu, Axel Jantsch
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory. 467-472 - Hamed Salah
Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder. 473-478
Network on Chip 2
- Liang Guang, Ethiopia Nigussie, Hannu Tenhunen
Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip. 481-486 - Sujay Deb
Comparative performance evaluation of wireless and optical NoC architectures. 487-492 - Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. 493-498 - Mohamed A. Abd El-Ghany
Power analysis for Asynchronous CLICHÉ Network-on-Chip. 499-504
Embedded Memory and Systems 2
- Satish Raghunath, Naveen Davanam, Lakshmi Deepika Bobbala, Byeong Kil Lee:
Way-load balancing scheme for mobile cache LRU replacement. 507-512 - Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli:
Exploiting large on-chip memory space through data recomputation. 513-518 - Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. 519-524
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