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2020 – today
- 2023
- [c119]Yixuan He, Minsu Choi, Kyung-Ki Kim, Yong-Bin Kim:
Low-Power Counters using Pathfinding Technique. ISOCC 2023: 69-70 - [c118]Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits. ISOCC 2023: 291-292 - 2022
- [c117]Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications. ISOCC 2022: 314-315 - [c116]Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
A Time-Domain Parallel Counter for Deep Learning Macro. ISOCC 2022: 346-347 - 2021
- [c115]Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
A Time-Domain Computing-In-Memory Micro using Ring Oscillator. ISOCC 2021: 107-108 - [c114]Youngwook Lee, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Stochastic Edge Detection for Fine-Grained Progressive Precision. ISOCC 2021: 119-120 - [c113]Cheolhyeong Park, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
FPGA-based Scalable Road Image Stochastic Denosing Approach. ISOCC 2021: 351-352 - [c112]Yixuan He, Yong-Bin Kim:
A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique. MWSCAS 2021: 999-1002 - 2020
- [c111]Elizabeth Amyouny, Yixuan He, Kyung Ki Kim, Yong-Bin Kim:
Peak Current Control Boost Converter with Time-Multiplex. ISOCC 2020: 105-106 - [c110]Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor. ISOCC 2020: 131-132 - [c109]Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach. ISOCC 2020: 282-283 - [c108]Yixuan He, Minsu Choi, Yong-Bin Kim:
A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing. MWSCAS 2020: 1007-1010
2010 – 2019
- 2019
- [c107]Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
Optimization of Null Convenction Logic Using Gate Diffusion Input. ISOCC 2019: 21-22 - [c106]Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
Area Efficient Multi-Threshold Null Convenction Logic. ISOCC 2019: 27-28 - [c105]Yixuan He, Kyung Ki Kim, Yong-Bin Kim:
Evaluations of Electronic Neuron Model for Low Power VLSI Implementation. ISOCC 2019: 206-207 - [c104]Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim:
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. ISOCC 2019: 241-242 - [c103]Gyunam Jeon, Yong-Bin Kim:
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. MWSCAS 2019: 694-697 - 2018
- [j37]Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim:
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. Integr. 63: 148-159 (2018) - [c102]Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing. ISOCC 2018: 218-219 - [c101]Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique. ISOCC 2018: 233-234 - [c100]Gyunam Jeon, Yong-Bin Kim:
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. MWSCAS 2018: 1-4 - [c99]Yun Seok Hong, Yong-Bin Kim:
Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell. MWSCAS 2018: 29-32 - 2017
- [j36]HeungJun Jeon, Kyung Ki Kim, Yong-Bin Kim:
Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs. Symmetry 9(1): 18 (2017) - [j35]Haiyang Zhu, Wenhua Yang, Gil Engel, Yong-Bin Kim:
A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 387-391 (2017) - [c98]Gyunam Jeon, Yong-Bin Kim:
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. ACM Great Lakes Symposium on VLSI 2017: 439-442 - [c97]Gyunam Jeon, Yong-Bin Kim:
A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. ISCAS 2017: 1-4 - [c96]Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Low-power null convention logic design based on modified gate diffusion input technique. ISOCC 2017: 21-22 - [c95]Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Variable bit truncation technique for approximate stochastic computing (ASC). ISOCC 2017: 73-74 - [c94]Gyunam Jeon, Yong-Bin Kim:
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap. ISOCC 2017: 244-245 - [c93]Yun Seok Hong, Yong-Bin Kim, Kyung Ki Kim:
Time-domain temperature sensor based on interlaced hysteresis delay cells. ISOCC 2017: 282-283 - [c92]Jing Yang, Yong-Bin Kim:
Global clock distribution on standing wave with CMOS active inductor loading. MWSCAS 2017: 128-131 - 2016
- [j34]Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi:
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. IEEE Trans. Computers 65(3): 781-790 (2016) - [c91]Yongsuk Choi, Yong-Bin Kim:
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC. ACM Great Lakes Symposium on VLSI 2016: 215-219 - [c90]Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Approximate stochastic computing (ASC) for image processing applications. ISOCC 2016: 31-32 - [c89]Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Hybrid GDI-NCL for area/power reduction. ISOCC 2016: 93-94 - [c88]Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Parallel decoding for multi-stage BCH decoder. ISOCC 2016: 107-108 - [c87]Yong-Bin Kim:
Integrated circuits design using carbon nanotube field effect transistor. ISOCC 2016: 125-126 - [c86]Yongsuk Choi, Yong-Bin Kim, In-Seok Jung:
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration. NATW 2016: 1-5 - [c85]Chen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim:
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. NATW 2016: 6-11 - 2015
- [j33]Haiyang Zhu, Ron Kapusta
, Yong-Bin Kim:
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1707-1715 (2015) - [c84]Yongsuk Choi, Yong-Bin Kim:
A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer. MWSCAS 2015: 1-4 - [c83]Ho Joon Lee, Yong-Bin Kim:
A process tolerant semi-self impedance calibration method for LPDDR4 memory controller. MWSCAS 2015: 1-4 - 2014
- [j32]Siva Kotipalli
Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. J. Electr. Comput. Eng. 2014: 837572:1-837572:13 (2014) - [j31]Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim:
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 497-506 (2014) - [c82]Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim:
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA. DFT 2014: 222-227 - [c81]In-Seok Jung, Yong-Bin Kim:
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch. DFT 2014: 276-280 - [c80]Jing Lu, Yong-Bin Kim:
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters. ACM Great Lakes Symposium on VLSI 2014: 75-76 - [c79]Ho Joon Lee, Yong-Bin Kim:
An area efficient low power high speed S-Box implementation using power-gated PLA. ACM Great Lakes Symposium on VLSI 2014: 93-94 - [c78]Yongsuk Choi, Yong-Bin Kim:
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers. ACM Great Lakes Symposium on VLSI 2014: 311-316 - [c77]Haiyang Zhu, Wenhua Yang, Nathan Egan, Yong-Bin Kim:
Calibration technique tracking temperature for current-steering digital-to-analog converters. MWSCAS 2014: 1-4 - [c76]In-Seok Jung, Yong-Bin Kim:
A novel self-calibration scheme for 12-bit 50MS/s SAR ADC. MWSCAS 2014: 5-8 - [c75]Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim:
Full custom implementation of a S-Box circuit architecture using power gated PLA structure. MWSCAS 2014: 294-297 - [c74]Yongsuk Choi, Chun-hsiang Chang, Hari Chauhan, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim:
A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers. MWSCAS 2014: 599-602 - 2013
- [c73]Ho Joon Lee, Yong-Bin Kim:
Low power Null Convention Logic circuit design based on DCVSL. MWSCAS 2013: 29-32 - [c72]Yongsuk Choi, HeungJun Jeon, Yong-Bin Kim:
A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method. MWSCAS 2013: 356-359 - [c71]Weifu Li, Yong-Bin Kim:
A high performance modulo 2n+1 squarer design based on carbon nanotube technology. MWSCAS 2013: 429-432 - [c70]In-Seok Jung, Marvin Onabajo, Yong-Bin Kim:
A 10-bit 64MS/s SAR ADC using variable clock period method. MWSCAS 2013: 1144-1147 - 2012
- [j30]Tina Marie Rookmaaker, Moon Seok Kim, Yong-Bin Kim:
Design and analysis of the quadfferential amplifier. Microelectron. J. 43(10): 697-707 (2012) - [j29]In-Seok Jung, Yong-Bin Kim:
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter. IEEE Trans. Ind. Electron. 59(2): 1154-1160 (2012) - [c69]Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han:
Hardening a memory cell for low power operation by gate leakage reduction. DFT 2012: 73-78 - [c68]HeungJun Jeon, Yong-Bin Kim:
A fully integrated switched-capacitor DC-DC converter with dual output for low power application. ACM Great Lakes Symposium on VLSI 2012: 83-86 - [c67]Jing Yang, Yong-Bin Kim:
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. ACM Great Lakes Symposium on VLSI 2012: 111-116 - [c66]In-Seok Jung, Yong-Bin Kim:
A low stand-by power start-up circuit for SMPS PWM controller. ACM Great Lakes Symposium on VLSI 2012: 251-254 - [c65]Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim:
A design and integration of Parametric Measurement Unit on to a 600MHz DCL. ISOCC 2012: 435-438 - [c64]Yongsuk Choi, Yong-Bin Kim, Fabrizio Lombardi:
Soft error masking latch for sub-threshold voltage operation. MWSCAS 2012: 25-28 - [c63]Jun Wu, Yong-Bin Kim, Minsu Choi:
Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system. MWSCAS 2012: 170-173 - [c62]Jun Wu, Yong-Bin Kim, Minsu Choi:
Post-configuration repair strategy for asynchronous nanowire crossbar system. MWSCAS 2012: 174-177 - [c61]Moon Seok Kim, Yong-Bin Kim, Kyung Ki Kim:
All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter. MWSCAS 2012: 326-329 - [c60]He Qi, Yong-Bin Kim, Minsu Choi:
A high speed low power modulo 2n+1 multiplier design using carbon-nanotube technology. MWSCAS 2012: 406-409 - [c59]Siva Pavan Kumar Kotipalli, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function. MWSCAS 2012: 410-413 - [c58]Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim:
On-chip HBD sensor for nanoscale CMOS technology. MWSCAS 2012: 434-437 - [c57]In-Seok Jung, Yong-Bin Kim, Fabrizio Lombardi:
A novel sort error hardened 10T SRAM cells for low voltage operation. MWSCAS 2012: 714-717 - [c56]Jing Lu, Jing Yang, Yong-Bin Kim, Joseph Ayers:
Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot. MWSCAS 2012: 782-785 - [c55]HeungJun Jeon, Yong-Bin Kim, Kyung Ki Kim:
A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss. MWSCAS 2012: 1060-1063 - 2011
- [j28]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 900-904 (2011) - [c54]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. ICCD 2011: 320-325 - [c53]Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim:
A design approach of a Parametric Measurement Unit on to a 600MHz DCL. ISOCC 2011: 446-449 - 2010
- [b1]Yong-Bin Kim:
Database Support for Top-Down Proteomics. University of Illinois Urbana-Champaign, USA, 2010 - [j27]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr. 43(2): 176-187 (2010) - [j26]HeungJun Jeon, Yong-Bin Kim, Minsu Choi:
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems. IEEE Trans. Instrum. Meas. 59(5): 1127-1133 (2010) - [j25]Jun Zhao, Yong-Bin Kim:
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. VLSI Design 2010: 946710:1-946710:11 (2010) - [c52]Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim:
Modelling a CNTFET with Undeposited CNT Defects. DFT 2010: 289-296 - [c51]Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi:
8Gb/s capacitive low power and high speed 4-PWAM transceiver design. ACM Great Lakes Symposium on VLSI 2010: 33-38 - [c50]HeungJun Jeon, Yong-Bin Kim:
A low-offset high-speed double-tail dual-rail dynamic latched comparator. ACM Great Lakes Symposium on VLSI 2010: 45-48 - [c49]Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi:
Performance assessment of analog circuits with carbon nanotube FET (CNFET). ACM Great Lakes Symposium on VLSI 2010: 163-166 - [c48]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Read-out schemes for a CNTFET-based crossbar memory. ACM Great Lakes Symposium on VLSI 2010: 167-170 - [c47]Jun Wu, Yong-Bin Kim, Minsu Choi:
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. ACM Great Lakes Symposium on VLSI 2010: 459-464 - [c46]Jun Zhao, Yong-Bin Kim:
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. ISQED 2010: 99-102 - [c45]Young Bok Kim, Yong-Bin Kim:
High speed and low power transceiver design with CNFET and CNT bundle interconnect. SoCC 2010: 152-157 - [c44]Jiaping Hu, Yong-Bin Kim, Joseph Ayers
A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. SoCC 2010: 281-284 - [c43]HeungJun Jeon, Yong-Bin Kim:
A CMOS low-power low-offset and high-speed fully dynamic latched comparator. SoCC 2010: 285-288
2000 – 2009
- 2009
- [j24]Cristiana Bolchini
Guest Editorial. J. Electron. Test. 25(1): 9-10 (2009) - [j23]Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi:
A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates. IEEE Trans. Instrum. Meas. 58(2): 401-410 (2009) - [j22]Kyung Ki Kim, Yong-Bin Kim:
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 517-528 (2009) - [c42]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A Novel Hardened Design of a CMOS Memory Cell at 32nm. DFT 2009: 58-64 - [c41]Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi:
Errors in DNA Self-Assembly by Synthesized Tile Sets. DFT 2009: 112-120 - [c40]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Soft-Error Hardening Designs of Nanoscale CMOS Latches. VTS 2009: 41-46 - 2008
- [j21]Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi:
Monomer Control for Error Tolerance in DNA Self-Assembly. J. Electron. Test. 24(1-3): 271-284 (2008) - [j20]Kyung Ki Kim, Yong-Bin Kim:
Standby power reduction using optimal supply voltage and body-bias voltage. IEICE Electron. Express 5(15): 556-561 (2008) - [j19]Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi:
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels. IEEE Trans. Ind. Informatics 4(2): 134-143 (2008) - [c39]Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi:
Checkpointing of Rectilinear Growth in DNA Self-Assembly. DFT 2008: 525-533 - [c38]Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A low leakage 9t sram cell for ultra-low power operation. ACM Great Lakes Symposium on VLSI 2008: 123-126 - [c37]Jun Zhao, Yong-Bin Kim:
A low power 32 nanometer CMOS digitally controlled oscillator. SoCC 2008: 183-186 - [c36]Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi:
Low power 8T SRAM using 32nm independent gate FinFET technology. SoCC 2008: 247-250 - [e2]Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor:
23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA. IEEE Computer Society 2008, ISBN 978-0-7695-3365-0 [contents] - 2007
- [j18]Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park:
Leakage Minimization Technique for Nanoscale CMOS VLSI. IEEE Des. Test Comput. 24(4): 322-330 (2007) - [j17]Kyung Ki Kim, Yong-Bin Kim:
Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology. IEICE Electron. Express 4(19): 606-611 (2007) - [j16]Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, Joseph Ayers
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot. Neurocomputing 71(1-3): 284-296 (2007) - [j15]Leonid Zamdborg, Richard D. LeDuc
ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry. Nucleic Acids Res. 35(Web-Server-Issue): 701-706 (2007) - [c35]Young Bok Kim, Yong-Bin Kim:
Fault Tolerant Source Routing for Network-on-Chip. DFT 2007: 12-20 - [c34]Ravi Bonam, Yong-Bin Kim, Minsu Choi:
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. DFT 2007: 161-169 - [c33]Yong-Bin Kim, Kyung Ki Kim, James T. Doyle:
A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. ISCAS 2007: 1149-1152 - [c32]Kyung Ki Kim, Yong-Bin Kim:
Optimal Body Biasing for Minimum Leakage Power in Standby Mode. ISCAS 2007: 1161-1164 - [e1]Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba:
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. IEEE Computer Society 2007, ISBN 0-7695-2885-6 [contents] - 2006
- [j14]Jihyun Lee, Yong-Bin Kim:
ASLIC: A low power CMOS analog circuit design automation. Integr. 39(3): 157-181 (2006) - [j13]Rui Tang, Fengming Zhang, Yong-Bin Kim:
Design metal-dot based QCA circuits using SPICE model. Microelectron. J. 37(8): 821-827 (2006) - [j12]Luca Schiano, Mariam Momenzadeh, Fengming Zhang, Young-Jun Lee, Thomas Kane, Solomon Max, Philip Perkins, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer:
Measuring the timing jitter of ATE in the frequency domain. IEEE Trans. Instrum. Meas. 55(1): 280-289 (2006) - [j11]Marco Ottavi
Evaluating the Yield of Repairable SRAMs for ATE. IEEE Trans. Instrum. Meas. 55(5): 1704-1712 (2006) - [j10]Woon Kang, Yong-Bin Kim, T. Doyle:
A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 229-240 (2006) - [c31]Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi:
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. DFT 2006: 89-97 - [c30]Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim:
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. DFT 2006: 98-106 - [c29]Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi:
Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. DFT 2006: 486-494 - [c28]Rui Tang, Yong-Bin Kim:
PWAM signalling scheme for high speed serial link transceiver design. ACM Great Lakes Symposium on VLSI 2006: 49-52 - [c27]Rui Tang, Yong-Bin Kim:
A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits. SoCC 2006: 119-122 - 2005
- [j9]Fengming Zhang, Rui Tang, Yong-Bin Kim:
SET-based nano-circuit simulation and design method using HSPICE. Microelectron. J. 36(8): 741-748 (2005) - [j8]Noh-Jin Park, K. M. George, Nohpill Park, Minsu Choi, Yong-Bin Kim, Fabrizio Lombardi:
Environmental-based characterization of SoC-based instrumentation systems for stratified testing. IEEE Trans. Instrum. Meas. 54(3): 1241-1248 (2005) - [c26]Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi:
On the Modeling and Analysis of Jitter in ATE Using Matlab. DFT 2005: 285-293 - [c25]Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi:
Data Dependent Jitter (DDJ) Characterization Methodology. DFT 2005: 294-304 - [c24]Rui Tang, Fengming Zhang, Yong-Bin Kim:
Quantum-dot cellular automata SPICE macro model. ACM Great Lakes Symposium on VLSI 2005: 108-111 - [c23]Rui Tang, Fengming Zhang, Yong-Bin Kim:
QCA-based nano circuits design [adder design example]. ISCAS (3) 2005: 2527-2530 - [c22]Jihyun Lee, Yong-Bin Kim:
ASLIC: A Low Power CMOS Analog Circuit Design Automation. ISQED 2005: 470-475 - 2004
- [j7]Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi:
Balanced dual-stage repair for dependable embedded memory cores. J. Syst. Archit. 50(5): 281-285 (2004) - [j6]J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch, Fabrizio Lombardi:
A CMOS subbandgap reference circuit with 1-v power supply voltage. IEEE J. Solid State Circuits 39(1): 252-255 (2004) - [j5]James T. Doyle, Young-Jun Lee, Yong-Bin Kim:
Fast and accurate DAC modeling techniques based on wavelet theory. Microelectron. J. 35(5): 451-460 (2004) - [j4]Richard D. LeDuc
ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry. Nucleic Acids Res. 32(Web-Server-Issue): 340-345 (2004) - [c21]Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi:
Fault tolerant clockless wave pipeline design. Conf. Computing Frontiers 2004: 350-356 - [c20]Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi:
Scan Test of IP Cores in an ATE Environment. DELTA 2004: 281-286 - [c19]Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer:
Reliability Modeling and Assurance of Clockless Wave Pipeline. DFT 2004: 442-450 - [c18]Fengming Zhang, Rui Tang, Yong-Bin Kim:
SET-based nano-circuit simulation and design method using HSPICE. ACM Great Lakes Symposium on VLSI 2004: 344-347 - [c17]Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, Alexander Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich:
Low power real time electronic neuron VLSI design using subthreshold technique. ISCAS (4) 2004: 744-747 - [c16]Young-Jun Lee, Yong-Bin Kim:
A fast and precise interconnect capacitive coupling noise model. ISCAS (2) 2004: 873-876 - [c15]Jihyun Lee, Young-Jun Lee, Yong-Bin Kim:
SRAM word-oriented redundancy methodology using built in self-repair. SoCC 2004: 219-222 - 2003
- [j3]Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi:
Guest Editors' Introduction: Clockless VLSI Systems. IEEE Des. Test Comput. 20(6): 5-8 (2003) - [j2]Woo Jin Kim, Yong-Bin Kim:
Automating Wave-Pipelined Circuit Design. IEEE Des. Test Comput. 20(6): 51-58 (2003) - [j1]Young-Jun Lee, Thomas Kane, Jong-Jin Lim, Young Jun Schiano, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max:
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment. IEEE Trans. Instrum. Meas. 52(6): 1749-1755 (2003) - [c14]James T. Doyle, Young-Jun Lee, Yong-Bin Kim:
An accurate DAC modeling technique based on wavelet theory. CICC 2003: 257-260 - [c13]Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri:
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. DFT 2003: 34- - [c12]Fengming Zhang, Young-Jun Lee, Thomas Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max, Phil Perkinson:
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. DFT 2003: 159-166 - [c11]Yeshwant Kolla, Yong-Bin Kim, John Carter:
A novel 32-bit scalable multiplier architecture. ACM Great Lakes Symposium on VLSI 2003: 241-244 - [c10]Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim:
A Novel Clocking Strategy for Dynamic Circuits. ISQED 2003: 307-312 - [c9]Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim:
Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. MSE 2003: 121-122 - [c8]Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri:
Optimal Spare Utilization in Repairable and Reliable Memory Cores. MTDT 2003: 64-71 - [c7]Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi:
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. NCA 2003: 341-350 - 2002
- [c6]Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park:
A Test-Vector Generation Methodology for Crosstalk Noise Faults. DFT 2002: 40-50 - [c5]Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri:
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. DFT 2002: 419-427 - [c4]Dae Woon Kang, Yong-Bin Kim:
Design flow of robust routed power distribution for low power ASIC. ISCAS (1) 2002: 181-184 - [c3]Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi:
Hardware/Software Co-Reliability of Configurable Digital Systems. PRDC 2002: 67-74 - 2001
- [c2]Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147
1990 – 1999
- 1997
- [c1]Yong-Bin Kim, Tom Chen:
A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. ASP-DAC 1997: 681-682
Coauthor Index
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