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25th LATS 2024: Maceio, Brazil
- 25th IEEE Latin American Test Symposium, LATS 2024, Maceio, Brazil, April 9-12, 2024. IEEE 2024, ISBN 979-8-3503-6555-9
- Victor O. Costa
, Fabio Benevenuti, Renan Menezes, Lidia Shibuya Sato, Luis Loures, Fernanda Lima Kastensmidt, Nemitala Added, Saulo G. Alberton, Vitor A. P. Aguiar, Nilberto H. Medina:
Heavy Ion-Induced Faults on Programmable UART Controllers Embedded into SRAM-Based FPGA. 1-6 - Acácio Cezar Aguiar Costa, Jarbas Aryel Nunes Da Silveira:
Case Study: Automated UPS Testing System for Final Test Applications in Industrial Environments. 1-2 - Leonardo Miceli, Elena-Ioana Vatajelu, Víctor H. Champac:
Fault Analysis for a MTJ-based Spiking Neural Network. 1-6 - Erik Larsson:
Embedded Tutorial: Access to On-chip Instruments via Functional Ports. 1-2 - Ievgen Kabin, Peter Langendoerfer, Zoya Dyka:
Exploiting Static Power Consumption in Side-Channel Analysis. 1-4 - Régis Leveugle, Nathan Hocquette, Charles Labarre, Romain Plumaugat, Loic Tcharoukian, Valentin Martinoli, Yannick Teglia:
Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study. 1-2 - Roua Boulifa, Giorgio Di Natale, Paolo Maistri:
Internal State Monitoring in RISC-V Microarchitectures for Security Purpose. 1-5 - Mohamed Mejri, Chandramouli N. Amarnath, Abhijit Chatterjee:
DeepER-HD: An Error Resilient HyperDimensional Computing Framework with DNN Front-End for Feature Selection. 1-6 - Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen:
Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation. 1-6 - Leonardo R. Gobatto, Fabio Benevenuti, Nemitala Added, Saulo G. Alberton, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Nilberto H. Medina, Fernanda Lima Kastensmidt, José Rodrigo Azambuja:
Reliability Assessment of Arm Cortex-M Processors under Heavy Ions and Emulated Fault Injection. 1-6 - Lucas Deutschmann
Data-Oblivious and Performant: On Designing Security-Conscious Hardware. 1-6 - Marko S. Andjelkovic, Milos Krstic:
Simulation-Based Analysis and Modeling of Generated Single Event Transient Pulse Width. 1-6 - Luis Ariel Mesa, Juan-David Guerrero-Balaguera
An Integrated Environment for the Reliability Assessment of CNNs Accelerators Implemented in FPGAs. 1-4 - Giuseppe Esposito, Juan-David Guerrero-Balaguera
Assessing the Reliability of Different Split Computing Neural Network Applications. 1-6 - Junchao Chen, Li Lu, Marko S. Andjelkovic, Fabian Luis Vargas, Milos Krstic:
Space Radiation Flux Driven Fault Injection for Evaluating Dynamic Mitigation Strategies. 1-6 - Alberto Bosio, M. Gomes, Fabio Pavanello, A. Porsia
Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks. 1-10 - Paolo Bernardi, Lorenzo Cardone, Tommaso Foscale:
Exploring trade-offs in multi-site wafer testing. 1-4 - Sophie Dupuis, Nassim Riadi
Logic Locking: Exploration of a new key-gate based on tristate logic. 1-6 - Salah Daddinounou, Elena-Ioana Vatajelu:
Study of a Spintronic-based STDP-trained SNN under Fabrication-induced Process Variability. 1-2 - K. Tahraoui, T. Vayssade, François Lefèvre, Laurent Latorre, Florence Azaïs:
Digital generation of single tone FM/PM test stimuli: a theoretical analysis. 1-6 - Gustavo Paz Platcheck
Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits. 1-6 - Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri:
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. 1-6 - Enrico Magliano, Alessio Carpegna, Alessandro Savino
A Micro Architectural Events Aware Real-Time Embedded System Fault Injector. 1-6 - Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli:
Invited Talk: Pros and Cons of Assertion Mining. 1-2 - María-Luisa Pinto-Salamanca, Josie E. Rodriguez Condia
Analyzing the Reliability of Stream Sparse Matrix-Vector Multiplication Accelerators: A High-Level Approach. 1-4 - Lorenzo Pfeifer, M. Gross, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators. 1-4 - Thiago Copetti, A. Chordia, Moritz Fieback
Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs. 1-6 - Nicola Dall'Ora
Analog Fault Simulation: Trends and Perspectives in Analog Hardware Description Languages. 1-2 - Rizwan Tariq Syed, Fabian Vargas, Marko S. Andjelkovic, Markus Ulbricht, Milos Krstic:
Aging and Soft Error Resilience in Reconfigurable CNN Accelerators Employing a Multi-Purpose On-Chip Sensor. 1-6 - Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Vmin Testing under Variations: Defect vs. Fault Coverage. 1-6 - Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab:
Keynote: Cost-Efficient Reliability for Edge-AI Chips. 1-2 - Fabian Vargas, Milos Krstic, Marko S. Andjelkovic, Markus Ulbricht, Junchao Chen:
Silicon Lifecycle Management Based on On-Chip Cross-Layer Sensing and Analytics for Space Applications. 1-6 - Stefano Aldegheri, Michele Boldo, Chiara Bozzini, Mirco De Marchi, Roberto Di Marco, Enrico Martini, Nicola Bombieri:
A Verification Platform for Human Pose Estimation Models. 1-6 - Hassen Aziza, Jérémy Postel-Pellerin, Moritz Fieback
Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing. 1-5 - Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. 1-6 - Jianan Wen
Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment. 1-6 - Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. 1-6
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