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ISQED 2013: Santa Clara, California, USA
- International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013. IEEE 2013, ISBN 978-1-4673-4951-2
- Mark M. Budnik, Rasit Onur Topaloglu
, Pallab Chatterjee, Keith A. Bowman
Welcome to ISQED 2013. - Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. 1-7 - Yue Hu, Shaoming Chen, Lu Peng, Edward Song, Jin-Woo Choi
Effective thermal control techniques for liquid-cooled 3D multi-core processors. 8-15 - Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
Reliability-constrained die stacking order in 3DICs under manufacturing variability. 16-23 - Yuriy Shiyanovskii, Christos A. Papachristou
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs. 24-29 - Nozad Karim:
New electrical design verification approach for 2.5D/3D package signal and power integrity. 30 - Jinbo Wan, Hans G. Kerkhoff:
An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations. 31-37 - Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang:
Impacts of NBTI and PBTI effects on ternary CAM. 38-45 - Yinhe Han, Song Jin, Jibing Qiu, Qiang Xu
On predicting NBTI-induced circuit aging by isolating leakage change. 46-52 - Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori:
Aging-aware timing analysis considering combined effects of NBTI and PBTI. 53-59 - Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar
Flexible data allocation for scratch-pad memories to reduce NBTI effects. 60-67 - Jongpil Jung, Kyungsu Kang, Giovanni De Micheli, Chong-Min Kyung:
Runtime 3-D stacked cache management for chip-multiprocessors. 68-72 - Nishit Ashok Kapadia, Sudeep Pasricha:
A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs. 73-79 - Dali Zhao, Houman Homayoun, Alexander V. Veidenbaum:
Temperature aware thread migration in 3D architecture with stacked DRAM. 80-87 - Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu:
A system-level solution for managing spatial temperature gradients in thinned 3D ICs. 88-95 - Conor O'Sullivan, Peter M. Levine, Siddharth Garg:
Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements. 96-103 - Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. 104-111 - Zhi Li, Jingweijia Tan, Xin Fu:
Hybrid CMOS-TFET based register files for energy-efficient GPGPUs. 112-119 - Shan Cao, Zhaolin Li, Zhixiang Chen
Compiler-assisted leakage energy optimization of media applications on stream architectures. 120-127 - Vinod Viswanath
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs. 128-134 - Jacob Murray, Rajath Hegde, Teng Lu, Partha Pratim Pande, Behrooz A. Shirazi:
Sustainable dual-level DVFS-enabled NoC with on-chip wireless links. 135-142 - Ivan Ratkovic, Oscar Palomar
On the selection of adder unit in energy efficient vector processing. 143-150 - Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy digital filter design based on controlled timing error acceptance. 151-157 - Ting Yu, Martin D. F. Wong
A novel and efficient method for power pad placement optimization. 158-163 - Nan Wang, Song Chen
Min-cut based leakage power aware scheduling in high-level synthesis. 164-169 - Yanzhi Wang, Maryam Triki, Xue Lin, Ahmed Chiheb Ammari
Hierarchical dynamic power management using model-free reinforcement learning. 170-177 - Jiaqi Yan, Zuying Luo, Liang Tang:
Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature. 178-183 - Na Gong, Jinhui Wang, Ramalingam Sridhar:
Application-driven power efficient ALU design methodology for modern microprocessors. 184-188 - Mrigank Sharad, Deliang Fan
Low power and compact mixed-mode signal processing hardware using spin-neurons. 189-195 - Chenyun Pan, Ahmet Ceyhan, Azad Naeemi
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. 196-202 - Ahmet Ceyhan, Azad Naeemi
Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. 203-209 - Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai:
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. 210-215 - Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. 216-222 - Mrigank Sharad, Karthik Yogendra, Kon-Woo Kwon, Kaushik Roy:
Design of ultra high density and low power computational blocks using nano-magnets. 223-230 - Jingwei Lu, Chiu-Wing Sham
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search. 231-238 - Jun Yong Shin, Nikil D. Dutt
Vision-inspired global routing for enhanced performance and reliability. 239-244 - Hanif Fatemi, Peivand Tehrani:
Crosstalk timing windows overlap in statistical static timing analysis. 245-251 - Soumyajit Chatterjee, Hafizur Rahaman
Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip. 252-256 - Martin D. F. Wong
Advances in wire routing. 257 - Shrikanth Ganapathy, Ramon Canal, Antonio González
Effectiveness of hybrid recovery techniques on parametric failures. 258-264 - Zheng Wang, Chao Chen, Anupam Chattopadhyay:
Fast reliability exploration for embedded processors via high-level fault injection. 265-272 - Jiyuan Luan, Michael DiVita:
Analysis and reliability test to improve the data retention performance of EPROM circuits. 273-277 - Valeriu Beiu
Enabling sizing for enhancing the static noise margins. 278-285 - Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
SRAM bit-line electromigration mechanism and its prevention scheme. 286-293 - Qiaosha Zou, Jing Xie, Yuan Xie:
Cost-driven 3D design optimization with metal layer reduction technique. 294-299 - Wulong Liu, Haixiao Du, Yu Wang
TSV-aware topology generation for 3D Clock Tree Synthesis. 300-307 - Rishik Bazaz, Jianyong Xie, Madhavan Swaminathan:
Electrical and thermal analysis for design exchange formats in three dimensional integrated circuits. 308-315 - Chih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan:
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning. 316-321 - Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, Shanq-Jang Ruan:
Configurable redundant via-aware standard cell design considering multi-via mechanism. 322-326 - Jifeng Chen, Mohammad Tehranipoor:
A novel flow for reducing clock skew considering NBTI effect and process variations. 327-334 - Youhua Shi
Suspicious timing error prediction with in-cycle clock gating. 335-340 - Senthil Arasu, Mehrdad Nourani, Vijay Reddy, John M. Carulli:
Performance entitlement by exploiting transistor's BTI recovery. 341-346 - Vita Pi-Ho Hu
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. 347-352 - Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. 353-358 - Avijit Dutta, Neil Tuttle, Krishnan Anandh:
Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance. 359-363 - Chung-Kai Hsu, Kun-Lin Tsai
A low power detection routing method for bufferless NoC. 364-367 - Jordan Bisasky, Houman Homayoun, Farhang Yazdani, Tinoosh Mohsenin:
A 64-core platform for biomedical signal processing. 368-372 - Ken Yano, Takanori Hayashida, Toshinori Sato
Improving timing error tolerance without impact on chip area and power consumption. 373-378 - Bahram N. Uchevler, Kjetil Svarstad
System-level modelling of dynamic reconfigurable designs using functional programming abstractions. 379-385 - Krishna Srinivasan, Jonathan Rosenfeld:
Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector. 386-390 - Shigetaka Kumashiro:
A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors. 391-397 - Kasyab P. Subramaniyan, Per Larsson-Edefors:
Manufacturable nanometer designs using standard cells with regular layout. 398-405 - Dhruva Ghai, Saraju P. Mohanty, Garima Thakral:
Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study. 406-411 - Daniela De Venuto
Low power sensor for temperature compensation in molecular biosensing. 412-415 - Rishi Todani, Ashis Kumar Mal:
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range. 416-421 - Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe:
Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. 422-429 - Matthew Cotter, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan:
Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications. 430-437 - Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda:
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. 438-441 - Jing Xie, Yang Du, Yuan Xie:
CPDI: Cross-power-domain interface circuit design in monolithic 3D technology. 442-447 - Hong Zhu, Volkan Kursun
Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. 448-453 - Bao Liu, Lu Wang:
Input-aware statistical timing analysis-based delay test pattern generation. 454-459 - Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Effect-cause intra-cell diagnosis at transistor level. 460-467 - Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue:
Framework for analog test coverage. 468-475 - Mohammad Shokrolah Shirazi, Brendan Morris
Fast FPGA-based fault injection tool for embedded processors. 476-480 - Ahish Mysore Somashekar, Spyros Tragoudas:
Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements. 481-486 - Sadiq M. Sait, Abdalrahman M. Arafeh:
Tabu search based cells placement in nanofabric architectures with restricted connectivity. 487-493 - Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng:
Relocatable and resizable SRAM synthesis for via configurable structured ASIC. 494-501 - Yuko Hara-Azumi, Hiroyuki Tomiyama:
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation. 502-507 - Sandeep Koranne:
Analysis of very large resistive networks using low distortion embedding. 508-515 - Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma:
Efficient translation validation of high-level synthesis. 516-523 - Young-Ho Gong, Hyung Beom Jang, Sung Woo Chung:
Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. 524-530 - Noemie Beringuier-Boher, David Hély
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology. 531-537 - Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. 538-545 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop. 546-551 - Dheepakkumaran Jayaraman, Spyros Tragoudas:
Performance validation through implicit removal of infeasible paths of the behavioral description. 552-557 - Richard Lee, Karim Abdel-Khalek, Samar Abdi, Frederic Risacher:
Early system level modeling of real-time applications on embedded platforms. 558-565 - Zihao Chen, Hailong Yao, Yici Cai:
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. 566-571 - Rahul Krishnan, Wei Wu, Fang Gong, Lei He:
Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy. 572-579 - Animesh Datta, Mohamed H. Abu-Rahma, Sachin Dileep Dasnurkar, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu:
Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology. 580-584 - Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake:
A comparator energy model considering shallow trench isolation stress by geometric programming. 585-590 - Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee:
Wire delay variability in nanoscale technology and its impact on physical design. 591-596 - Hiromitsu Awano
Multi-trap RTN parameter extraction based on Bayesian inference. 597-602 - Nishit Ashok Kapadia, Sudeep Pasricha:
VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands. 603-610 - Alexandra Aguiar, Carlos Moratelli
A virtualization approach for MIPS-based MPSoCs. 611-618 - Yi Xiang, Sudeep Pasricha:
Thermal-aware semi-dynamic power management for multicore systems with energy harvesting. 619-626 - Yiqiang Ding, Wei Zhang:
On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. 627-634 - Yanzhi Wang, Shuang Chen, Hadi Goudarzi, Massoud Pedram:
Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model. 635-642 - Yong Zou, Sudeep Pasricha:
Reliability-aware and energy-efficient synthesis of NoC based MPSoCs. 643-650 - Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
CMOS inverter delay model based on DC transfer curve for slow input. 651-657 - Errikos Lourandakis, Stefanos Stefanou, Konstantinos Nikellis, Sotiris Bantas:
RF passive device modeling and characterization in 65nm CMOS technology. 658-664 - Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand:
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. 665-669 - Jai Narayan Tripathi
Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization. 670-675 - Dheepakkumaran Jayaraman, Spyros Tragoudas:
A method to determine the sensitization probability of a non-robustly testable path. 676-681 - Suming Lai, Peng Li:
A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation. 682-688 - Amaravati Anvesha, Maryam Shojaei Baghini:
A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning. 689-695 - Nicolo Testi, Yang Xu:
A 0.2nJ/sample 0.01mm2 ring oscillator based temperature sensor for on-chip thermal management. 696-702 - Shinichi Nishizawa, Tohru Ishihara
Analysis and comparison of XOR cell structures for low voltage circuit design. 703-708 - Kwang Sub Yoon, Keon Lee:
A CMOS high dimming ratio power-LED driver with a preloading inductor current method. 709-713 - Satyanarayana Telikepalli, Madhavan Swaminathan, David C. Keezer
Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling. 714-718 - Xin Fu, Tao Li, José A. B. Fortes:
Reliable Express-Virtual-Channel-based network-on-chip under the impact of technology scaling. 719-726 - Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Thiago Asis:
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops. 727-732 - Dinesh Ganta, Leyla Nazhandali:
Easy-to-build Arbiter Physical Unclonable Function with enhanced challenge/response set. 733-738
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