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Ivan Ratkovic
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2020 – today
- 2023
- [j5]Zoran Babovic
, Branislav Bajat
Research in computing-intensive simulations for nature-oriented civil-engineering and related scientific fields, using machine learning and big data: an overview of open problems. J. Big Data 10(1): 73 (2023) - [j4]Zoran Babovic
Teaching computing for complex problems in civil engineering and geosciences using big data and machine learning: synergizing four different computing paradigms and four different management domains. J. Big Data 10(1): 89 (2023) - 2021
- [c10]Veljko M. Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing. MECO 2021: 1-6 - 2020
- [i1]Veljko Milutinovic, Milos Kotlar, Ivan Ratkovic, Nenad Korolija, Miljan Djordjevic, Kristy Yoshimoto, Erik Klem, Mateo Valero:
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips. CoRR abs/2009.10593 (2020)
2010 – 2019
- 2018
- [j3]Ivan Ratkovic
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 639-652 (2018) - 2017
- [j2]Milan Stanic, Oscar Palomar
An Integrated Vector-Scalar Design on an In-Order ARM Core. ACM Trans. Archit. Code Optim. 14(2): 17:1-17:26 (2017) - 2016
- [b1]Ivan Ratkovic:
On the design of power- and energy-efficient functional units for vector processors. Polytechnic University of Catalonia, Spain, 2016 - [c9]Milan Stanic, Oscar Palomar
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. PACT 2016: 447-448 - [c8]Milan Stanic, Oscar Palomar
Towards low-power embedded vector processor. Conf. Computing Frontiers 2016: 339-342 - [c7]Ivan Ratkovic, Oscar Palomar
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. ISLPED 2016: 362-367 - 2015
- [j1]Ivan Ratkovic, Nikola Bezanic, Osman S. Ünsal
Chapter One - An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques. Adv. Comput. 98: 1-57 (2015) - [c6]Ivan Ratkovic, Oscar Palomar
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. ISVLSI 2015: 19-26 - [c5]Milovan Duric, Milan Stanic, Ivan Ratkovic, Oscar Palomar
Imposing coarse-grained reconfiguration to general purpose processors. SAMOS 2015: 42-51 - 2014
- [c4]Milan Stanic, Oscar Palomar
VALib and SimpleVector: tools for rapid initial research on vector architectures. Conf. Computing Frontiers 2014: 7:1-7:10 - [c3]Milan Stanic, Oscar Palomar
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. HPCS 2014: 47-54 - [c2]Ivan Ratkovic, Oscar Palomar
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. ISVLSI 2014: 118-123 - 2013
- [c1]Ivan Ratkovic, Oscar Palomar
On the selection of adder unit in energy efficient vector processing. ISQED 2013: 143-150
Coauthor Index
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