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ISQED 2006: San Jose, California, USA
- 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. IEEE Computer Society 2006, ISBN 0-7695-2523-7
Introduction
- Welcome Notes.
- Organizing Committee.
- Technical Subcommittees.
- Steering/Advisory Committee.
- Conference at a Glance.
ISQED Tutorials
- Rajiv V. Joshi, Kaustav Banerjee, André DeHon:
Tutorial 1: Emerging Technologies for VLSI Design. 4 - Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar:
Tutorial II: Variability and Its Impact on Design. 5
ISQED Panel Discussion
- Michael Santarini, Pallab K. Chatterjee:
Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?. 7
ISQED Plenary Session
- Risto Suoranta:
Modular service-oriented platform architecture - a key enabler to SoC design quality. 11-13 - Tohru Furuyama:
Deep sub-100 nm Design Challenges. 13-14 - Di Ma:
Successful IP Business Models. 15-18
Session 1A: Variation Aware Timing
- Praveen Ghanta, Sarma B. K. Vrudhula:
Variational Interconnect Delay Metrics for Statistical Timing Analysis. 19-24 - Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene:
Statistically Aware SRAM Memory Array Design. 25-30 - Zhiyu Liu, Volkan Kursun
:
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. 31-36 - Andrew B. Kahng, Bao Liu, Xu Xu:
Constructing Current-Based Gate Models Based on Existing Timing Library. 37-42 - Zhuo Feng, Peng Li, Jiang Hu:
Efficient Model Update for General Link-Insertion Networks. 43-50
Session 1B: High-Level Design Verification
- Miroslav N. Velev
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. 51-56 - Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
EFSM Manipulation to Increase High-Level ATPG Effectiveness. 57-62 - Indradeep Ghosh
A Technique for Estimating the Difficulty of a Formal Verification Problem. 63-70 - Chandan Karfa
A Formal Verification Method of Scheduling in High-level Synthesis. 71-78
Session 1C: Physical Planning
- Anand Rajaram, David Z. Pan:
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. 79-84 - Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study. 85-91 - Narender Hanchate, Nagarajan Ranganathan:
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. 92-97 - Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. 98-104
ISQED Luncheon Speech
- Michael Keating:
Simplicity and Executability: Cornerstones of Quality. 105
Session 2A: Robust Device and Circuit Design
- Yogesh Singh Chauhan
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. 109-114 - Jin He, Xing Zhang, Ganggang Zhang, Mansun Chan, Yangyuan Wang:
A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs. 115-120 - Brian Swahn, Soha Hassoun:
METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. 121-126 - Jin He, Xing Zhang, Ganggang Zhang, Yangyuan Wang:
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs. 127-132 - Chong Zhao, Sujit Dey:
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). 133-140
Session 2B: Power, Noise and Timing Issues in DSM Designs
- Soheil Ghiasi, Po-Kuan Huang:
Probabilistic Delay Budgeting for Soft Realtime Applications. 141-146 - Jindrich Zejda, Li Ding:
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. 147-152 - Nahmsuk Oh, Li Ding, Alireza Kasnavi:
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop. 153-159 - Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar:
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. 159-164 - Deniz Dal
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. 165-170 - Andrew Havlir, David Z. Pan:
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. 171-178
Session 2C: Memory Analysis
- Fadi J. Kurdahi
System-Level SRAM Yield Enhancement. 179-184 - Young-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, Jeong-Taek Kong:
Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model. 185-189 - R. Venkatraman, R. Castagnetti, S. Ramesh:
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. 190-195 - Makoto Sugihara, Tohru Ishihara
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. 196-203 - Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka
SRAM Local Bit Line Access Failure Analyses. 204-209 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Impact of NBTI on SRAM Read Stability and Design for Reliability. 210-218
Session 2D: Posters
- Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas:
Minimizing FPGA Reconfiguration Data at Logic Level. 219-224 - Kaiping Zeng, Sorin A. Huss:
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. 225-230 - Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses. 231-236 - Xinjie Wei, Yici Cai, Xianlong Hong:
Clock Skew Scheduling Under Process Variations. 237-242 - Qikai Chen, Mesut Meterelliyoz, Kaushik Roy:
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. 243-248 - Rasit Onur Topaloglu
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems. 249-253 - Peng Li:
Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage. 254-259 - C. Tabery, M. Craig, Gert Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs:
Process Window and Device Variations Evaluation using Array-Based Characterization Circuits. 260-265 - Xiongfei Meng, Resve A. Saleh, Karim Arabi:
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. 266-271 - Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. 272-277 - Seongkyun Shin, Yungseon Eo:
Non-Physical Pseudo-Wave-Based Modal Decoupling Technique of Multi- Coupled Co-Planar Transmission Lines with Homogeneous Dielectric Media. 278-283 - Krishna Srinivasan, P. Muthana, Rohan Mandrekar, Ege Engin
Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages. 284-291 - Cheng Zhuo, Jiang Hu, Kangsheng Chen:
An Improved AMG-based Method for Fast Power Grid Analysis. 290-295 - Miroslav N. Velev
Formal Verification of Pipelined Microprocessors with Delayed Branches. 296-299 - Arkan Abdulrahman, Spyros Tragoudas:
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. 300-305 - Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Random Variables. 306-311 - Ali Bastani, Charles A. Zukowski:
A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. 312-317 - Zhiyu Liu, Volkan Kursun
Leakage Biased Sleep Switch Domino Logic. 318-323 - Randy Bach, Bob Davis, Rich Laubhan:
Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology. 324-329 - Sajid Baloch, Tughrul Arslan, Adrian Stoica
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices. 330-345 - Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys:
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. 334-339 - Jia Wang, Hai Zhou, Ping-Chih Wu:
Processing Rate Optimization by Sequential System Floorplanning. 340-345 - Zile Wei, Donald Chai, A. Richard Newton, Andreas Kuehlmann:
Fast Boolean Matching with Don't Cares. 346-351 - Krishnan Srinivasan, Karam S. Chatha:
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. 352-357 - Praveen Bhojwani, Rabi N. Mahapatra:
Core Network Interface Architecture and Latency Constrained On-Chip Communication. 358-363 - Vyas Krishnan, Srinivas Katkoori
Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. 364-369 - Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. 370-375 - Concepción Sanz, Manuel Prieto
System-level process variability compensation on memory organizations of dynamic applications: a case study. 376-382 - Biye Wang, Lili He, Morris Jones:
A low input, low-power dissipation CMOS ADC. 383-386 - J. Balachandran, Steven Brebels, Geert Carchon, Walter De Raedt
Constant Impedance Scaling Paradigm for Scaling LC transmission lines. 387-392 - Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. 393-400
Session 3A: Interconnect Analysis and Optimization
- Min Chen, Yu Cao:
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design. 401-406 - Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra:
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk. 407-412 - Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu:
Compact Reduced Order Modeling for Multiple-Port Interconnects. 413-418 - Taeyong Je, Yungseon Eo:
Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching. 419-424 - Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah
Reducing the Data Switching Activity on Serial Link Buses. 425-432
Session 3B: Digital Test and Diagnosis Techniques
- Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Efficient Multiphase Test Set Embedding for Scan-based Testing. 433-438 - Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Evaluation of Collapsing Methods for Fault Diagnosis. 439-444 - Yu Huang:
On N-Detect Pattern Set Optimization. 445-450 - Li-Chung Hsu, Hung-Ming Chen:
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. 451-456 - Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas:
An Improved Method for Identifying Linear Dependencies in Path Delay Faults. 457-462 - Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test. 463-472
Session 3C: Back of Line DFM
- Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte:
Yield Improvement by Local Wiring Redundancy. 473-478 - Takumi Uezono, Kenichi Okada, Kazuya Masu:
Via Distribution Model for Yield Estimation. 479-484 - Lawrence S. Melvin III, Daniel N. Zhang, Kirk J. Strozewski, Skye Wolfer:
The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design. 485-490 - Robert C. Aitken:
DFM Metrics for Standard Cells. 491-496 - Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson:
Yield Enhancement Methodology for CMOS Standard Cells. 497-502 - Hsin-Chyh Hsu, Ming-Dou Ker:
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. 503-506
ISQED Panel Discussion 2
- Ron Wilson, David Overhauser:
Who is really responsible for quality throughout the design process?. 507
ISQED Plenary Session 2
- Raul Camposano:
Adding Manufacturability to the Quality of Results. 511 - Changhyun Kim:
Future Memory Technology Trends and Challenges. 513 - H.-S. Philip Wong:
Device and Technology Challenges for Nanoscale CMOS. 515-518
Session 4A: Analog Test and Self-Checking Design
- Adam Matthews:
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard. 519-524 - Qingqi Dou, Jacob A. Abraham:
Jitter Decomposition by Time Lag Correlation. 525-530 - Amit Laknaur, Haibo Wang:
Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits. 531-536 - Daniela De Venuto
Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs. 537-542 - José Luis Catalano, Gabriela Peretti
Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder Filters. 543-550
Session 4B: Power Aware Designs and Memory Management
- Ozcan Ozturk, Mahmut T. Kandemir:
Data Replication in Banked DRAMs for Reducing Energy Consumption. 551-556 - Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson:
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. 557-563 - Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos:
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. 564-569 - Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk:
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs. 570-575 - Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu:
Shared Scratch-Pad Memory Space Management. 576-584
Session 4C: Technologies for Robust Design
- Wei Zhao, Yu Cao:
New Generation of Predictive Technology Model for Sub-45nm Design Exploration. 585-590 - M. Thomas, J. Pathak, J. Payne, Friedrich Peter Leisenberger, Ewald Wachmann, Gregor Schatzberger, Andreas Wiesner, Martin Schrems:
A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications. 591-596 - Tai-Xiang Lai, Ming-Dou Ker:
Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. 597-602 - Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Analysis of Process Variation's Effect on SRAM's Read Stability. 603-610 - Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester:
Logic SER Reduction through Flipflop Redesign. 611-616 - Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar:
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. 617-624
Session 5A: IC-Package Design Challenges
- Greg M. Link, Narayanan Vijaykrishnan:
Thermal Trends in Emerging Technologies. 625-632 - Kanak Agarwal, Kevin J. Nowka
Power Gating with Multiple Sleep Modes. 633-637 - Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. 638-643 - Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif:
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. 644-649 - Mark M. Budnik, Kaushik Roy:
Minimizing Ohmic Loss in Future Processor IR Events. 650-658
Session 5B: IP, Interoperability: Design Optimization
- Anand Pramod Kulkarni, Thomas J. Grebinski:
mTest: An Industry-Wide Database of VLSI Layouts for Quality Control. 659-664 - Sanghamitra Roy
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. 665-670 - Guangyu Sun, Zhiqiang Gao, Yi Xu:
A Watermarking System for IP Protection by Buffer Insertion Technique. 671-675 - Anand Pramod Kulkarni, Thomas J. Grebinski:
Partial Selective Encryption: An Improved System for Protecting VLSI Design Data in the OASIS format. 676-681 - Dimitri Kagaris, Themistoklis Haniotakis:
Transistor-Level Optimization of Supergates. 682-690
Session 5C: DSM Interconnect Challenges
- Andrew B. Kahng, Kambiz Samadi, Puneet Sharma:
Study of Floating Fill Impact on Interconnect Capacitance. 691-696 - Karen Chow:
The Challenges and Impact of Parasitic Extraction at 65 nm. 697-702 - Laureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret:
Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation. 703-708 - Changhao Yan, Wenjian Yu, Zeyi Wang:
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. 709-716
Session 6A: Leakage Analysis and Optimization
- Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. 717-722 - Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang:
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. 723-728 - Behnam Amelifard, Massoud Pedram, Farzan Fallah:
Low-leakage SRAM Design with Dual V_t Transistors. 729-734 - Akhilesh Kumar, Mohab Anis:
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance. 735-740 - Chanseok Hwang, Chang Woo Kang, Massoud Pedram:
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. 741-746 - Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
Impact of Gate-Length Biasing on Threshold-Voltage Selection. 747-754
Session 6B: System Level Designs and Reliability Models
- Bin Zhang, Wei-Shen Wang, Michael Orshansky:
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. 755-760 - Lee Barford:
Diagnosis and Design for Diagnosability for Internet Routers. 761-768 - Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao:
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. 769-774 - Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada:
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. 775-780 - Riad Ben Mouhoub, Omar Hammami:
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC. 781-788
Session 6C: Modeling for DFM
- Artur Balasinski:
Question: DRC or DfM ? Answer: FMEA and ROI. 789-794 - Usha Narasimha, Binu Abraham, N. S. Nagaraj:
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. 795-800 - Sridhar Tirumala, Yuri Mahotin, Xiao Lin, Victor Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, Dipu Pramanik:
Bringing Manufacturing into Design via Process-Dependent SPICE Models. 801-806 - Victor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins:
Stress-Aware Design Methodology. 807-812 - Peter Wright, Minghui Fan:
A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit. 813-817
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