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Usha Narasimha
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2000 – 2009
- 2007
- [c6]Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan:
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. ISSCC 2007: 262-601 - 2006
- [c5]Usha Narasimha, Binu Abraham, N. S. Nagaraj:
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. ISQED 2006: 795-800 - [c4]Usha Narasimha, Anthony M. Hill, N. S. Nagaraj:
SmartExtract: Accurate Capacitance Extraction for SOC Designs. VLSI Design 2006: 786-789 - 2005
- [c3]N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill:
BEOL variability and impact on RC extraction. DAC 2005: 758-759 - 2004
- [c2]Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich:
A 800 MHz System-on-Chip for Wireless Infrastructure Applications. VLSI Design 2004: 381- - 2003
- [c1]N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell:
Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED 2003: 163-168
Coauthor Index
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