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Wei-Shen Wang
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2000 – 2009
- 2009
- [j4]Michael Orshansky, Wei-Shen Wang:
Statistical analysis of circuit timing using majorization. Commun. ACM 52(8): 95-100 (2009) - 2007
- [j3]Wei-Shen Wang, Michael Orshansky:
Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electron. 3(1): 1-12 (2007) - 2006
- [j2]Wei-Shen Wang, Michael Liu, Michael Orshansky:
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electron. 2(1): 1-7 (2006) - [j1]Wei-Shen Wang, Michael Orshansky:
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2976-2988 (2006) - [c5]Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky:
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC 2006: 161-166 - [c4]Wei-Shen Wang, Michael Orshansky:
Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD 2006: 884-890 - [c3]Bin Zhang, Wei-Shen Wang, Michael Orshansky:
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED 2006: 755-760 - [c2]Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang:
Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC 2006: 1645-1649 - 2004
- [c1]Michael Liu, Wei-Shen Wang, Michael Orshansky:
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED 2004: 2-7
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