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20th FPL 2010: Milano, Italy
- International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy. IEEE Computer Society 2010, ISBN 978-0-7695-4179-2
Poster Session I
- Isa Uzun, Mark Heron, Alun Morgan, Guenther Rehm:
An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source. 1-4 - Fabio Garzia, Waqar Hussain
, Jari Nurmi
Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core. 5-9 - Salvatore Pontarelli
Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems. 10-14 - Henning Sahlbach, Sean Whitty, Oliver Bende, Rolf Ernst:
A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture. 15-18 - Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. 19-24 - Qigang Wang, Rolf Kassa, Wenbo Shen, Nelson Ijih, Bhushan Chitlur, Michael Konow, Dong Liu, Arthur Sheiman, Prabhat Gupta:
An FPGA Based Hybrid Processor Emulation Platform. 25-30 - Alexander Choong, Rami Beidas, Jianwen Zhu:
Parallelizing Simulated Annealing-Based Placement Using GPGPU. 31-34 - Fatma Abouelella, Karel Bruneel, Dirk Stroobandt:
Efficiently Generating FPGA Configurations through a Stack Machine. 35-39
Regular Expression Matching on FPGA
- SangKyun Yun, KyuHee Lee:
Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA. 40-43 - Francesco Bruschi, Marco Paolieri, Vincenzo Rana
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching. 44-49 - Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna:
Automation Framework for Large-Scale Regular Expression Matching on FPGA. 50-55
Multimedia
- Weirong Jiang
Real-Time Classification of Multimedia Traffic Using FPGA. 56-63 - Petr Matas, Eva Dokládalová
Parallel Hardware Implementation of Connected Component Tree Computation. 64-69 - Andrés Otero
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. 70-76
Random Numbers and Cryptography
- David B. Thomas, Wayne Luk:
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. 77-82 - Ralf Zimmermann, Tim Güneysu
High-Performance Integer Factoring with Reconfigurable Devices. 83-88 - Chalermpol Saiprasert, Christos-Savvas Bouganis
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA. 89-94
Scheduling
- Ye Lu, Sakir Sezer, John V. McCanny:
Advanced Multithreading Architecture with Hardware Based Scheduling. 95-100 - Sungmin Bae, Narayanan Vijaykrishnan:
Thermal Gradient Aware Clock Skew Scheduling for FPGAs. 101-106 - Philip Garcia, Kyle Rupnow
A Reconfigurable Computing Scheduler Optimized for Multicore Systems. 107-112
GPU, CPU and FPGA
- Brian Leung, Chih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra:
An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs. 113-118 - David Huw Jones
GPU Versus FPGA for High Productivity Computing. 119-124 - Doris Chen, Deshanand P. Singh
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). 125-132
Reconfigurable Architecture and Cryptography
- Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu
Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware. 133-138 - Lyonel Barthe, Pascal Benoit, Lionel Torres:
Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures. 139-144 - Kostas Theocharoulis, Ioannis Papaefstathiou
Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking. 145-150
Poster Session II
- Masayuki Suzuki, Yoshifumi Tanida, Tsutomu Maruyama:
Detecting Patterns in Various Size and Angle Using FPGA. 151-154 - Kentaro Kokufuta, Tsutomu Maruyama:
Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA. 155-158 - Hung-Manh Pham, Sébastien Pillement
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC. 159-162 - Stephen Wray, Wayne Luk, Peter R. Pietzuch
Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine. 163-166 - Hiroaki Niitsuma, Tsutomu Maruyama:
Sum of Absolute Difference Implementations for Image Processing on FPGAs. 167-170 - Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu:
Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction. 171-174 - Amir Hossein Gholamipour, Fadi J. Kurdahi
Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters. 175-178 - Florian Devic, Lionel Torres, Benoît Badrignans:
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA. 179-182 - Cédric Killian, Camel Tanougast
Online Routing Fault Detection for Reconfigurable NoC. 183-186
Self-Aware and Adaptable Systems
- Filippo Sironi, Marco Triverio, Henry Hoffmann, Martina Maggio
Self-Aware Adaptation in FPGA-based Systems. 187-192 - Kenneth M. Zick, John P. Hayes:
Self-Test and Adaptation for Random Variations in Reliability. 193-198 - Nicolas Ngan, Geoffroy Marpeaux, Eva Dokládalová
Memory System for a Dynamically Adaptable Pixel Stream Architecture. 199-204
Reconfigurable and Customized Processors
- Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro Furuta:
Test Compression for Dynamically Reconfigurable Processors. 205-210 - Wen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, Zhiliang Hong:
A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks. 211-216 - Otto Esko, Pekka Jääskeläinen
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. 217-222
Communication Infrastructure
- Heiner Giefers
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. 223-228 - Leandro Möller, Peter Fischer, Fernando Moraes
Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. 229-233 - Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch:
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. 234-239
PhD Forum
- Norbert Abel:
Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration. 240-243 - Paulo Ferreira
Erlang Inspired Hardware. 244-246 - Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
IP Based Configurable SIMD Massively Parallel SoC. 247-250 - Pedro V. Santos, José C. Alves:
FPGA Based Engines for Genetic and Memetic Algorithms. 251-254 - Stephanie Drzevitzky:
Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration. 255-258 - Akhilesh Kumar, Mohab Anis:
Robust FPGA Design under Variations. 259-262 - João Bispo
On Identifying Segments of Traces for Dynamic Compilation. 263-266 - Adriano K. Sanches, João M. P. Cardoso
On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates. 267-270
Memories and Application Interfaces
- Robin Panda, Jimmy Xu, Scott Hauck:
Software Managed Distributed Memories in MPPAs. 271-278 - Martin Schoeberl
Design and Implementation of Real-Time Transactional Memory. 279-284 - Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat
Rapid Application Development on Multi-processor Reconfigurable Systems. 285-290
New Trends and Solutions in Programmable Logic
- Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge:
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs. 291-297 - Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. 298-303 - Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. 304-309
Design Methodologies and Tools
- Dam Sunwoo, Gene Y. Wu, Nikhil A. Patil, Derek Chiou:
PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems. 310-317 - Thomas B. Preußer, Rainer G. Spallek:
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. 318-325 - Felipe Restrepo-Calle
Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA. 326-331
Poster Session III
- Marcus Ritt
A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs. 332-335 - Antonin Hermanek, Michal Kunes, Milan Tichý:
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. 336-339 - Ruediger Willenberg, Zamira Daw, Christian Englert, Marcus Vetter:
Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities. 340-345 - Nathan Naber, Thomas Getz, Yong Kim, James Petrosky:
Real-Time Fault Detection and Diagnostics Using FPGA-based Architectures. 346-351 - Krzysztof Jozwik
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. 352-355 - Hari Angepat, Gage Eads, Christopher Craik, Derek Chiou:
NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping. 356-359 - Edward Fernandez, Walid A. Najjar
Exploration of Short Reads Genome Mapping in Hardware. 360-363 - Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. 364-367
Reconfigurable Technology
- Vijay K. Sirigir, Khawla Alzoubi
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA. 368-373 - Sumanta Chaudhuri
High Density Asynchronous LUT Based on Non-volatile MRAM Technology. 374-379 - Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck:
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. 380-387
Applications
- Shahrukh Athar
Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization. 388-393 - Weirong Jiang
Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA. 394-399 - Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane
FPGA Implementations of the Round Two SHA-3 Candidates. 400-407
Benchmarking and Architecture Evaluation
- Daniel W. Chang, Christipher D. Jenkins, Philip C. Garcia, Syed Zohaib Gilani, Paula Aguilera, Aishwarya Nagarajan, Michael J. Anderson, Matthew A. Kenny, Sean M. Bauer, Michael J. Schulte, Katherine Compton:
ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing. 408-413 - Kris Gaj, Jens-Peter Kaps
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. 414-421 - Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
Pipelined FPGA Adders. 422-427
Poster Session IV
- Edward A. Stott, Justin S. J. Wong
Degradation Analysis and Mitigation in FPGAs. 428-433 - Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong
A Karatsuba-Based Montgomery Multiplier. 434-437 - Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Using Hard Macros to Reduce FPGA Compilation Time. 438-441 - Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song:
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing. 442-447 - Miltiadis Smerdis, Panagiotis Dagritzikos, Grigorios Chrysos, Euripides Sotiriades, Apostolos Dollas:
Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data. 448-451 - Matthias Meier, Michael Engel, Matthias Steinkamp, Olaf Spinczyk:
LavA: An Open Platform for Rapid Prototyping of MPSoCs. 452-457 - Mingjie Lin, Ilia A. Lebedev, John Wawrzynek:
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. 458-463 - Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin:
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. 464-468 - Gerald Hempel, Christian Hochberger, Andreas Koch:
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor. 469-474
HLL-based Design
- Hagen Gädke-Lütjens, Benjamin Thielmann, Andreas Koch:
A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation. 475-482 - Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo
Early Prediction of Hardware Complexity in HLL-to-HDL Translation. 483-488
Arithmetic Units
- Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier. 489-495 - Gustavo Sutter
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. 496-501
Special Applications
- Ángel Quirós-Olozábal
Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers. 502-507 - Maki Yasuda, Minoru Watanabe:
Dynamically Reconfigurable Vision-Chip Architecture. 508-512
Reconfigurable Hardware for Networking
- Christopher E. Neely, Gordon J. Brebner
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. 513-518 - Faisal Khan, Maya B. Gokhale, Chen-Nee Chuah
FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns. 519-524 - Michael Dreschmann, Michael Hübner, Moritz Röger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold
Reconfigurable Hardware for Power-over-Fiber Applications. 525-531
Synthesis and Placement
- Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu:
Efficient FPGA Resynthesis Using Precomputed LUT Structures. 532-537 - Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. Wirthlin:
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. 538-543 - Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. 544-549
FPGA-based Accelerators
- Ricardo S. Ferreira, Julio C. Goldner Vendramini:
FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks. 550-555 - Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. 556-561 - Stefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, Volker Lindenstruth:
An FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics. 562-567
Poster Session V
- Muhammad Shafiq
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators. 568-573 - Florent de Dinechin, Mioara Joldes, Bogdan Pasca
Multiplicative Square Root Algorithms for FPGAs. 574-577 - Matteo Pusceddu, Simone Ceccolini, Gianluca Palermo
A Compact Transactional Memory Multiprocessor System on FPGA. 578-581 - Deborah Goshorn, Junguk Cho, Ryan Kastner
Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications. 582-587 - Anthony Brandon, Ioannis Sourdis, Georgi Nedeltchev Gaydadjiev
General Purpose Computing with Reconfigurable Acceleration. 588-591 - Sascha Mühlbach, Martin Brunner, Christopher Roblee, Andreas Koch:
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology. 592-595 - Christian Beckhoff, Dirk Koch, Jim Tørresen:
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration. 596-601 - Atukem Nabina, José L. Núñez-Yáñez:
Dynamic Reconfiguration Optimisation with Streaming Data Decompression. 602-607 - Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. 608-611
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