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Gustavo Sutter
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2020 – today
- 2023
- [j13]Tobias Alonso
, Gustavo Sutter
Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2620-2624 (2023) - 2021
- [j12]Tobias Alonso
LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS. IEEE Access 9: 106606-106626 (2021)
2010 – 2019
- 2019
- [j11]Martín Vázquez, Lucas Leiva
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. Microprocess. Microsystems 64: 143-158 (2019) - [c22]Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo:
Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. FPL 2019: 286-292 - 2018
- [c21]Tobias Alonso
Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. FPL 2018: 355-359 - [c20]Gustavo Sutter, Mario Ruiz
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig 2018: 1-6 - 2017
- [c19]Mario Ruiz
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. ReConFig 2017: 1-6 - [c18]Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. ReConFig 2017: 1-6 - 2016
- [j10]Mario Ruiz
Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. IEEE Commun. Mag. 54(3): 80-87 (2016) - [c17]Mario Ruiz
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. FPL 2016: 1-4 - [c16]Mario Ruiz
FPGA-based encrypted network traffic identification at 100 Gbit/s. ReConFig 2016: 1-6 - [c15]Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. ReConFig 2016: 1-6 - 2015
- [c14]Mario Ruiz
Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. ReConFig 2015: 1-6 - 2014
- [j9]Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
Bridging the gap between hardware and software open source network developments. IEEE Netw. 28(5): 13-19 (2014) - [c13]Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. ReConFig 2014: 1-6 - 2013
- [j8]Diego Sanchez-Roman, Victor Moreno
FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. J. Syst. Archit. 59(3): 135-143 (2013) - [j7]Gustavo Sutter
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Trans. Ind. Electron. 60(1): 217-225 (2013) - [c12]Marco Forconesi, Gustavo Sutter
Accurate and flexible flow-based monitoring for high-speed networks. FPL 2013: 1-4 - 2012
- [b1]Jean-Pierre Deschamps, Gustavo Sutter, Enrique Cantó:
Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering 149, Springer 2012, ISBN 978-94-007-2986-5, pp. 1-459 - [j6]Iván González
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. J. Syst. Archit. 58(6-7): 247-256 (2012) - 2011
- [j5]Diego Sanchez-Roman, Gustavo Sutter
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Des. Test Comput. 28(4): 28-37 (2011) - [j4]Elias Todorovich, Gustavo Sutter
Selected Papers from the Southern Programmable Logic Conference (SPL2010). Int. J. Reconfigurable Comput. 2011: 714761:1 (2011) - [j3]Gustavo Sutter
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Trans. Ind. Electron. 58(7): 3101-3109 (2011) - 2010
- [j2]Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter:
High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfigurable Comput. 2010: 219764:1-219764:14 (2010) - [c11]Gustavo Sutter
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL 2010: 496-501
2000 – 2009
- 2009
- [c10]Gustavo Sutter
High speed fixed point dividers for FPGAs. FPL 2009: 448-452 - [c9]Gustavo Sutter
FPGA Implementations of BCD Multipliers. ReConFig 2009: 36-41 - [c8]Martín Vázquez, Gustavo Sutter
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ReConFig 2009: 42-47 - [c7]Carlos Minchola, Gustavo Sutter
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. ReConFig 2009: 59-64 - 2008
- [j1]Gustavo Sutter, Richard Katz:
Selected Papers from SPL 2008: Programmable Logic and Applications. Int. J. Reconfigurable Comput. 2008: 921921:1-921921:2 (2008) - 2005
- [c6]Jean-Pierre Deschamps, Gustavo Sutter
Finite Field Division Implementation. FPL 2005: 670-674 - 2004
- [c5]Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps:
Comparative Study of SRT-Dividers in FPGA. FPL 2004: 209-220 - [c4]Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo:
Power Aware Dividers in FPGA. PATMOS 2004: 574-584 - 2002
- [c3]Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo:
A Tool for Activity Estimation in FPGAs. FPL 2002: 340-349 - [c2]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
FSM Decomposition for Low Power in FPGA. FPL 2002: 350-359 - [c1]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS 2002: 363-370
Coauthor Index
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