default search action
MEMSYS 2016: Alexandria, VA, USA
- Bruce L. Jacob:
Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016. ACM 2016, ISBN 978-1-4503-4305-3
Issues in High Performance Computing
- Darko Zivanovic
, Milan Radulovic
Large-Memory Nodes for Energy Efficient High-Performance Computing. 3-9 - Aditya M. Deshpande, Jeffrey T. Draper:
A New Metric to Measure Cache Utilization for HPC Workloads. 10-17 - Nilmini Abeyratne, Hsing Min Chen, Byoungchan Oh
Checkpointing Exascale Memory Systems with Existing Memory Technologies. 18-29 - Brice Goglin
Exposing the Locality of Heterogeneous Memory Architectures to HPC Applications. 30-39 - Kazi Asifuzzaman
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC. 40-49 - Tia Newhall, E. Ryerson Lehman-Borer, Benjamin Marks:
Nswap2L: Transparently Managing Heterogeneous Cluster Storage Resources for Fast Swapping. 50-61 - Shang Li, Po-Chun Huang, David Banks, Max DePalma, Ahmed Elshaarany, K. Scott Hemmert, Arun Rodrigues, Emily Ruppel, Yitian Wang, Jim Ang, Bruce L. Jacob:
Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems. 62-73
Nonvolatile Main Memories and DRAM Caches, Part I
- Dong Chen, Chencheng Ye, Chen Ding
Write Locality and Optimization for Persistent Memory. 77-87 - Simon D. Hammond, Arun F. Rodrigues, Gwendolyn R. Voskuilen:
Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out. 88-93 - Krishna T. Malladi, Manu Awasthi, Hongzhong Zheng:
DRAMPersist: Making DRAM Systems Persistent. 94-95 - Jim Stevens, Paul Tschirhart, Bruce L. Jacob:
Fast full system memory checkpointing with SSD-aware memory controller. 96-98 - Shuai Che, Arkaprava Basu, Jonathan Gallmeier:
Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors: A Programmer's View. 99-103 - Amin Farmahini Farahani, David Roberts, Nuwan Jayasena:
Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems. 104-118
Hybrid Memory Cube and Alternative DRAM Channels
- Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström:
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. 121-132 - Ke Zhang, Lei Yu, Yisong Chang, Ran Zhao, Hongxia Zhang, Lixin Zhang, Mingyu Chen, Sally A. McKee:
Co-DIMM: Inter-Socket Data Sharing via a Common DIMM Channel. 133-141 - Juri Schmidt, Holger Fröning, Ulrich Brüning:
Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube. 142-150 - Pranith Kumar, Lifeng Nai, Hyesoon Kim:
Analyzing Consistency Issues in HMC Atomics. 151-152 - John D. Leidel, Yong Chen
Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes. 153-163 - Zehan Cui, Tianyue Lu, Sally A. McKee, Mingyu Chen, Haiyang Pan, Yuan Ruan:
Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems. 164-176 - Xi Wang, John D. Leidel, Yong Chen
Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. 177-187
Nonvolatile Main Memories and DRAM Caches, Part II
- Seunghee Shin, Sihong Kim, Yan Solihin:
Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache. 191-203 - Gwendolyn Voskuilen, Arun F. Rodrigues, Simon D. Hammond:
Analyzing allocation behavior for multi-level memory. 204-207 - Mohsen Imani, Yan Cheng, Tajana Rosing:
Processing Acceleration with Resistive Memory-based Computation. 208-210 - Paul Tschirhart, Jim Stevens, Zeshan Chishti, Bruce L. Jacob:
The Case for Associative DRAM Caches. 211-219 - Mahzabeen Islam, Soumik Banerjee, Mitesh R. Meswani, Krishna M. Kavi:
Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization. 220-231 - Jacob Brock, Chencheng Ye, Chen Ding
Replacement Policies for Heterogeneous Memories. 232-237 - Wei Wang, Wen Pan, Tao Xie, Deng Zhou:
How Many MLCs Should Impersonate SLCs to Optimize SSD Performance? 238-247
Thinking Outside the Box
- Xiaochen Guo, Aviral Shrivastava
Languages Must Expose Memory Heterogeneity. 251-256 - Matthias Jung
ConGen: An Application Specific DRAM Memory Controller Generator. 257-267 - Yin Li, Hao Wang, Xiaoqing Zhao, Hongbin Sun, Tong Zhang:
Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud. 268-278 - Arkaprava Basu, Sooraj Puthoor, Shuai Che, Bradford M. Beckmann:
Software Assisted Hardware Cache Coherence for Heterogeneous Processors. 279-288 - Rishiraj A. Bheda, Thomas M. Conte
Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging. 289-294 - Patrick Siegl, Rainer Buchty, Mladen Berekovic
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory. 295-308
Improving the DRAM Device Architecture
- Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside
HAPPY: Hybrid Address-based Page Policy in DRAMs. 311-321 - XianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang:
AWARD: Approximation-aWAre Restore in Further Scaling DRAM. 322-324 - Krishna T. Malladi, Uksong Kang, Manu Awasthi, Hongzhong Zheng:
DRAMScale: Mechanisms to Increase DRAM Capacity. 325-326 - Hao Wang, Yin Li, Xuebin Zhang, Xiaoqing Zhao, Hongbin Sun, Tong Zhang:
On the Use of DRAM with Unrepaired Weak Cells in Computing Systems. 327-337 - Aditya Agrawal, Mike O'Connor
CLARA: Circular Linked-List Auto and Self Refresh Architecture. 338-349 - Nagendra Gulur, R. Govindarajan, Mahesh Mehendale:
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. 350-361 - Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. 362-373
Issues and Interconnects for 2.5D and 3D Packaging
- Paolo Grani
Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip. 377-386 - Syed Minhaj Hassan, Sudhakar Yalamanchili:
Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems. 387-394 - Manish Gupta, David Roberts, Mitesh R. Meswani, Vilas Sridharan, Dean M. Tullsen
Reliability and Performance Trade-off Study of Heterogeneous Memories. 395-401 - Yuxiong Zhu, Borui Wang, Dong Li, Jishen Zhao:
Integrated Thermal Analysis for Processing In Die-Stacking Memory. 402-414 - Majed Valad Beigi, Gokhan Memik:
TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid Caches. 415-426
Some Amazingly Cool Physical Experiments
- Khaled Z. Ibrahim, Farzad Fatollahi-Fard, David Donofrio, John Shalf
Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes. 429-436 - G. Scott Lloyd, Maya B. Gokhale:
Evaluating the feasibility of storage class memory as main memory. 437-441 - Dietmar Fey, Marc Reichenbach
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. 442-454 - Spencer Desrochers, Chad Paradis, Vincent M. Weaver:
A Validation of DRAM RAPL Power Measurements. 455-470 - Matthias Jung, Carl Christian Rheinländer, Christian Weis, Norbert Wehn:
Reverse Engineering of DRAMs: Row Hammer with Crosshair. 471-476
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-04 20:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: