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Test Data Compression: The System Integrator's Perspective

Published: 03 March 2003 Publication History

Abstract

Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integratorýs standpoint considering a core based SOC environment. The proposed analysis addresses four parameters: compression ratio, test application time, area overhead and power dissipation. Based on our analysis, some future research directions are given which can lead to an easier integration of TDC in the SOC design flow and to further improve the four parameters.

References

[1]
{1} Virginia Polytechnic Institute and State University. http://www.ee.vt.edu/~ha/cadtools/cadtools.html.
[2]
{2} I. Bayraktaroglu and A. Orailoglu. Test Volume and Application Time Reduction Through Scan Chain Concealment. In DAC, volume 38, pp 151-155, June 2001.
[3]
{3} B. Bottoms. The third millennium's test dilemma. IEEE Design & Test of Computers, 15(4):7-11, Oct. 1998.
[4]
{4} F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In ISCAS, pp 1929-1934, May 1989.
[5]
{5} A. Chandra and K. Chakrabarty. Combining Low-Power Scan Testing and Test Data Compression for System-on-a-chip. In DAC, volume 38, pp 113-120, June 2001.
[6]
{6} A. Chandra and K. Chakrabarty. Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. In VTS, pp 114-121, Apr. 2001.
[7]
{7} R. Dorsch and H.-J. Wunderlich. Tailoring ATPG for Embedded Testing. In ITC, pp 530-537, Oct. 2001.
[8]
{8} P. T. Gonciari, B. Al-Hashimi, and N. Nicolici. Improving Compression Ratio, Area overhead, and Test Application Time in System-ona-Chip Test Data Compression/Decompression. In DATE, pp 604- 611, Mar. 2002.
[9]
{9} P. T. Gonciari, B. Al-Hashimi, and N. Nicolici. Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. In ITC, pp 64-73, Oct. 2002.
[10]
{10} P. T. Gonciari, B. Al-Hashimi, and N. Nicolici. Reducing Synchronization Overhead in Test Data Compression Environments. In Digest of Papers ETW, pp 147-152, May 2002.
[11]
{11} P. T. Gonciari, B. Al-Hashimi, and N. Nicolici. Useless Memory Allocation: Problems and Solutions. In VTS, pp 423-430, Apr. 2002.
[12]
{12} H. Ichihara, K. Kinoshita, I. Pomeranz, and S. Reddy. Test Transformation to Improve Compaction by Statistical Encoding. In VLSI Design, pp 294-299, Jan. 2000.
[13]
{13} ITRS. The International Technology Roadmap for Semiconductors, 2001 Edition. http://public.itrs.net/.
[14]
{14} A. Jas, J. Ghosh-Dastidar, and N. A. Touba. Scan Vector Compression/Decompression Using Statistical Coding. In VTS, pp 114-121, Apr. 1999.
[15]
{15} A. Khoche and J. Rivoir. I/O Bandwidth Bottleneck for Test: Is it Real ? In Proceedings of Test Resource Partitioning Workshop, pp 2.3-1-2.3-6, Nov. 2000.
[16]
{16} B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater. A Smart BIST Variat with Guaranteed Encoding. In ATS, pp 325-330, Nov. 2001.
[17]
{17} E. J. Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. JETTA, 18(4), Aug. 2002.
[18]
{18} N. Nicolici and B. M. Al-Hashimi. Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. IEEE Computer, 51(6):721-734, June 2002.
[19]
{19} J. Rajski. DFT for High-Quality Low Cost Manufacturing Test. In ATS, pp 3-8, Nov. 2001.
[20]
{20} S. Reda and A. Orailoglu. Reducing Test Application Time Through Test Data Mutation Encoding. In DATE, pp 387-393, Mar. 2002.
[21]
{21} P. M. Rosinger, P. T. Gonciari, B. Al-Hashimi, and N. Nicoli. Analysing trade-offs in scan power and test data compression for system-on-a-chip. IEE Proceedings, Computers and Digital Techniques , 149(4):188-196, July 2002.
[22]
{22} Synopsys Inc. Design compiler reference manual, 2001.
[23]
{23} S. Wang and S. Gupta. ATPG for heat dissipation minimization during test application. IEEE Computer, 47(2):256-262, Feb. 1998.
[24]
{24} B. G. West. At-Speed Structural Test. In ITC, pp 795-800, Sept. 1999.
[25]
{25} L. Whetsel. Adapting Scan Architectures for Low Power Operation. In ITC, pp 863-872, Oct. 2000.
[26]
{26} Y. Zorian. A distributed BIST control scheme for complex VLSI devices. In VTS, pp 4-9, 1993.

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cover image ACM Conferences
DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
March 2003
1112 pages
ISBN:0769518702

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Published: 03 March 2003

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