Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Page 599
Abstract
A novel approach for testing embedded memories in complexsystems-on-a-chip (SOCs) is presented. The proposedsolution aims to balance the usage of the existing on-chipresources and dedicated design for test (DFT) hardwaresuch that the functional power constraints are not exceededduring test while trading-off the testing time againstDFT area and performance overhead. The suitability ofsoftware-centric and hardware-centric approaches for embeddedmemory testing is examined and to combine the advantagesof both directions, a new built-in self-test (BIST)-basedmethod, called hardware/software co-testing, is introduced.The proposed solution is programmable, scalableand guarantees low routing overhead.
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Index Terms
- Hardware/Software Co-testing of Embedded Memories in Complex SOCs
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November 2003
899 pages
ISBN:1581137621
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IEEE Computer Society
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Published: 09 November 2003
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