Article

Delay Fault Testing of Core-Based Systems-on-a-Chip

Authors:

Nicola NicoliciAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10744

Published: 03 March 2003 Publication History

Abstract

Existing approaches for modular manufacturing testing of core-based systems-on-a-chip (SOCs) do not provide any explicit mechanism for high quality two-pattern tests required for performance validation through delay fault testing. This paper proposes a new approach for broadside delay fault testing of core-based SOCs, by adapting the existing solutions for automatic test pattern generation and design for test support, test access mechanism division and test scheduling.

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Cited By

Karimi NChakrabarty KGupta PPatil SRosenstiel WMacii E(2012)Test generation for clock-domain crossing faults in integrated circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492811(406-411)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492811
Jiang LHuang LXu QBenini LDe Micheli GAl-Hashimi BMueller W(2009)Test architecture design and optimization for three-dimensional SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874672(220-225)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874672
Wang ZChakrabarty KGoessel MGielen G(2006)Test set enrichment using a probabilistic fault model and the theory of output deviationsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131832(1270-1275)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131832

Index Terms

Delay Fault Testing of Core-Based Systems-on-a-Chip
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware

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cover image ACM Conferences

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Cited By

Karimi NChakrabarty KGupta PPatil SRosenstiel WMacii E(2012)Test generation for clock-domain crossing faults in integrated circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492811(406-411)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492811
Jiang LHuang LXu QBenini LDe Micheli GAl-Hashimi BMueller W(2009)Test architecture design and optimization for three-dimensional SoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874672(220-225)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874672
Wang ZChakrabarty KGoessel MGielen G(2006)Test set enrichment using a probabilistic fault model and the theory of output deviationsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131832(1270-1275)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131832

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