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Dae-Hyun Kim 0003
Person information
- affiliation: Samsung Electronics, Hwaseong, Korea
- affiliation (PhD): Georgia Institute of Technology, Atlanta, GA, USA
Other persons with the same name
- Daehyun Kim (aka: Dae Hyun Kim, Dae-Hyun Kim) — disambiguation page
- Dae Hyun Kim 0004
(aka: Dae-Hyun Kim 0004, Daehyun Kim 0004) — Washington State University (WSU), School of Electrical Engineering and Computer Science, Pullman, WA, USA (and 1 more)
- Daehyun Kim 0005
- Daehyun Kim 0006
- Daehyun Kim 0001 — Intel Corporation, Santa Clara, CA, USA
- Daehyun Kim 0002
- Daehyun Kim 0007
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2020 – today
- 2022
- [c14]Dae-Hyun Kim
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC 2022: 448-450 - 2021
- [j12]Chang-Kyo Lee
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. IEEE J. Solid State Circuits 56(1): 212-224 (2021) - [c13]Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. ISSCC 2021: 346-348 - 2020
- [c12]Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC 2020: 382-384
2010 – 2019
- 2019
- [j11]Dae-Hyun Kim
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1640-1651 (2019) - [c11]Youngsok Kim, Joonsung Kim, Dongju Chae, Daehyun Kim, Jangwoo Kim:
μLayer: Low Latency On-Device Inference Using Cooperative Single-Layer Acceleration and Processor-Friendly Quantization. EuroSys 2019: 45:1-45:15 - 2018
- [c10]Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, Onur Mutlu:
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks. ASPLOS 2018: 316-331 - [c9]Kexin Yang, Rui Zhang, Taizhi Liu, Dae Hyun Kim
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology. DCIS 2018: 1-6 - 2017
- [b1]Dae-Hyun Kim:
Design methodologies for scalable and reliable memory systems. Georgia Institute of Technology, Atlanta, GA, USA, 2017 - [j10]Dae-Hyun Kim
Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test. Microelectron. Reliab. 76-77: 47-52 (2017) - [j9]Kexin Yang, Taizhi Liu, Rui Zhang, Dae Hyun Kim
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits. Microelectron. Reliab. 76-77: 81-86 (2017) - [j8]Dae-Hyun Kim
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2045-2058 (2017) - [c8]Dae-Hyun Kim
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes. VTS 2017: 1-6 - 2016
- [j7]Woongrae Kim, Chang-Chih Chen, Dae Hyun Kim
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2521-2534 (2016) - [c7]Dae Hyun Kim
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. VTS 2016: 1-6 - 2015
- [j6]Dae-Hyun Kim
Architectural Support for Mitigating Row Hammering in DRAM Memories. IEEE Comput. Archit. Lett. 14(1): 9-12 (2015) - [j5]Dae Hyun Kim
AVERT: An elaborate model for simulating variable retention time in DRAMs. Microelectron. Reliab. 55(9-10): 1313-1319 (2015) - [j4]Soonyoung Cha
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. Microelectron. Reliab. 55(9-10): 1404-1411 (2015) - [j3]Dae Hyun Kim
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. Microelectron. Reliab. 55(9-10): 2113-2118 (2015) - [c6]Moinuddin K. Qureshi, Dae-Hyun Kim
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. DSN 2015: 427-437 - 2013
- [c5]Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi:
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. ISCA 2013: 72-83 - 2011
- [j2]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. IEEE J. Solid State Circuits 46(1): 107-118 (2011) - [c4]Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. ISSCC 2011: 498-500 - 2010
- [c3]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC 2010: 434-435
2000 – 2009
- 2008
- [j1]Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. IEEE J. Solid State Circuits 43(1): 121-131 (2008) - [c2]Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. ISSCC 2008: 278-279 - 2007
- [c1]Jeong-Don Ihm, Seung-Jun Bae, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. ISSCC 2007: 492-617
Coauthor Index
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last updated on 2024-11-21 20:27 CET by the dblp team
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