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Journal Articles
- 2024
- [j38]Saikat Basu
, Arnav Das
FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation. J. Syst. Softw. 214: 112085 (2024) - [j37]Ritajit Majumdar, Amit Saha
Intermediate qutrit-assisted Toffoli gate decomposition with quantum error correction. Quantum Inf. Process. 23(2): 42 (2024) - 2023
- [j36]Sudipta Paul
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. Integr. 92: 66-76 (2023) - [j35]Ritajit Majumdar, Susmita Sur-Kolay:
Designing Ternary Quantum Error Correcting Codes from Binary Codes. J. Multiple Valued Log. Soft Comput. 40(1-2): 179-201 (2023) - [j34]Manobendra Nath Mondal
Test Optimization in Memristor Crossbars Based on Path Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 294-307 (2023) - 2022
- [j33]Amit Saha
Faster search of clustered marked states with lackadaisical quantum walks. Quantum Inf. Process. 21(8): 275 (2022) - 2021
- [j32]Sudipta Paul
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. IET Circuits Devices Syst. 15(4): 310-329 (2021) - [j31]Debasri Saha, Susmita Sur-Kolay:
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud. ACM Trans. Embed. Comput. Syst. 20(1): 1:1-1:25 (2021) - 2020
- [j30]Somoballi Ghoshal, Sourav Banu, Amlan Chakrabarti, Susmita Sur-Kolay
3D reconstruction of spine image from 2D MRI slices along one axis. IET Image Process. 14(12): 2746-2755 (2020) - 2019
- [j29]Debasri Saha
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1742-1750 (2019) - 2017
- [j28]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan
CABA: Continuous Authentication Based on BioAura. IEEE Trans. Computers 66(5): 759-772 (2017) - [j27]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan
Wearable Medical Sensor-Based System Design: A Survey. IEEE Trans. Multi Scale Comput. Syst. 3(2): 124-138 (2017) - [j26]Arsalan Mosenia
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. IEEE Trans. Multi Scale Comput. Syst. 3(4): 255-268 (2017) - 2016
- [j25]Debasri Saha, Susmita Sur-Kolay:
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip. IET Comput. Digit. Tech. 10(3): 110-118 (2016) - [j24]Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan
Physiological Information Leakage: A New Frontier in Health Information Security. IEEE Trans. Emerg. Top. Comput. 4(3): 321-334 (2016) - 2015
- [j23]Gautam K. Das, Minati De
Approximation algorithms for maximum independent set of a unit disk graph. Inf. Process. Lett. 115(3): 439-446 (2015) - [j22]Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay:
Quantum Ternary Circuit Synthesis Using Projection Operations. J. Multiple Valued Log. Soft Comput. 24(1-4): 73-92 (2015) - [j21]Mehran Mozaffari Kermani
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. IEEE J. Biomed. Health Informatics 19(6): 1893-1905 (2015) - [j20]Arsalan Mohsen Nia, Mehran Mozaffari Kermani
Energy-Efficient Long-term Continuous Personal Health Monitoring. IEEE Trans. Multi Scale Comput. Syst. 1(2): 85-98 (2015) - [j19]Debasri Saha, Susmita Sur-Kolay:
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 801-809 (2015) - [j18]Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha:
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1221-1234 (2015) - 2014
- [j17]Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay:
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. 10(3): 443-454 (2014) - 2012
- [j16]Debasri Saha, Susmita Sur-Kolay:
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1749-1757 (2012) - 2011
- [j15]Pritha Banerjee
Cone-based placement for field programmable gate arrays. IET Comput. Digit. Tech. 5(1): 49-62 (2011) - [j14]Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay:
Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 8-17 (2011) - [j13]Debasri Saha, Susmita Sur-Kolay:
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection. VLSI Design 2011: 731957:1-731957:10 (2011) - 2010
- [j12]Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey:
Test pattern generation for droop faults. IET Comput. Digit. Tech. 4(4): 274-284 (2010) - [j11]Debasri Saha, Susmita Sur-Kolay:
Robust intellectual property protection of VLSI physical design. IET Comput. Digit. Tech. 4(5): 388-399 (2010) - 2009
- [j10]Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay:
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9(2): 711-724 (2009) - [j9]Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Droop sensitivity of stuck-at fault tests. IET Comput. Digit. Tech. 3(2): 175-193 (2009) - [j8]Susmita Sur-Kolay, Satyajit Banerjee, Srabani Mukhopadhyaya
The Double Digest Problem: finding all solutions. Int. J. Bioinform. Res. Appl. 5(5): 570-592 (2009) - [j7]Pritha Banerjee
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 651-661 (2009) - [j6]Pritha Banerjee
FPGA placement using space-filling curves: Theory meets practice. ACM Trans. Embed. Comput. Syst. 9(2): 12:1-12:23 (2009) - 2007
- [j5]Amlan Chakrabarti, Susmita Sur-Kolay:
Nearest Neighbour based Synthesis of Quantum Boolean Circuits. Eng. Lett. 15(2): 356-361 (2007) - [j4]Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das:
Hierarchical partitioning of VLSI floorplans by staircases. ACM Trans. Design Autom. Electr. Syst. 12(1): 7:1-7:19 (2007) - 2004
- [j3]Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Manhattan-diagonal routing in channels and switchboxes. ACM Trans. Design Autom. Electr. Syst. 9(1): 75-104 (2004) - 2001
- [j2]Parthasarathi Dasgupta, Susmita Sur-Kolay:
Slicible rectangular graphs and their optimal floorplans. ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001) - 1998
- [j1]Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and optimal sizing of floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 126-135 (1998)
Conference and Workshop Papers
- 2024
- [c69]Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Susmita Sur-Kolay:
Machine Learning based Decoding of Heavy Hexagonal QECC for Asymmetric Quantum Noise. ISVLSI 2024: 246-251 - [c68]Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay:
Optimized QAOA ansatz circuit design for two-body Hamiltonian problems. VLSID 2024: 396-401 - 2023
- [c67]Archan Ghosh, Debgandhar Ghosh, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay:
Segmentation and Labeling of Vertebra Using SegFormer Architecture. CVIP (2) 2023: 160-171 - 2022
- [c66]Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay:
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs. ITC 2022: 494-498 - [c65]Santlal Prajaprati, Manobendra Nath Mondal, Susmita Sur-Kolay:
Memristive Neural Network with Efficient In-Situ Supervised Training. SOCC 2022: 1-6 - [c64]Kritanta Saha, Pritha Banerjee
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. VLSI-SoC 2022: 1-6 - [c63]Kritanta Saha, Sudipta Paul, Pritha Banerjee
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. VLSID 2022: 138-143 - 2021
- [c62]Somoballi Ghoshal, Partha Bhowmick, Amlan Chakrabarti, Susmita Sur-Kolay, Sanjukta Chakravorti
3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil. IVCNZ 2021: 1-6 - 2020
- [c61]Ritajit Majumdar, Susmita Sur-Kolay:
Special Session: Quantum Error Correction in Near Term Systems. ICCD 2020: 9-12 - [c60]Ritajit Majumdar, Susmita Sur-Kolay:
Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost. ISMVL 2020: 34-39 - [c59]Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar. ISVLSI 2020: 494-499 - 2019
- [c58]Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test. ATS 2019: 25-30 - [c57]Sudipta Paul, Pritha Banerjee
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. ISVLSI 2019: 212-217 - [c56]Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. VLSID 2019: 383-388 - 2017
- [c55]Sudipta Paul, Pritha Banerjee
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. ICCD 2017: 411-414 - [c54]Ritajit Majumdar, Saikat Basu
A Method to Reduce Resources for Quantum Error Correction. RC 2017: 151-161 - [c53]Debasri Saha, Susmita Sur-Kolay:
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. VLSID 2017: 372-377 - 2016
- [c52]Saikat Basu
An efficient synthesis method for ternary reversible logic. ISCAS 2016: 2306-2309 - [c51]Bapi Kar
An early global routing framework for uniform wire distribution in SoCs. SoCC 2016: 139-144 - [c50]Bapi Kar
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID 2016: 595-596 - 2015
- [c49]Bapi Kar
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI 2015: 107-112 - [c48]Sudipta Paul, Pritha Banerjee
Flare reduction in EUV Lithography by perturbation of wire segments. VLSI-SoC 2015: 7-12 - 2014
- [c47]Debasri Saha, Susmita Sur-Kolay:
Trusted sharing of intellectual property in electronic hardware design. WESS 2014: 9:1-9:3 - [c46]Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay:
Energy-Aware H.264 Decoding. ICDCIT 2014: 200-211 - [c45]Sudhindu Bikash Mandal
Synthesis of Ternary Grover's Algorithm. ISMVL 2014: 184-189 - [c44]Sumit Saha, Bapi Kar
A novel architecture for QPSK modulation based on time-mode signal processing. VDAT 2014: 1-6 - [c43]Bapi Kar
Global Routing Using Monotone Staircases with Minimal Bends. VLSID 2014: 369-374 - 2013
- [c42]Arighna Deb, Debesh K. Das, Susmita Sur-Kolay:
Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED 2013: 143-147 - [c41]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Global routing using monotone staircase channels. ISVLSI 2013: 90-95 - [c40]Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay, Prasenjit Basu, Bhaskar J. Karmakar:
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures. VDAT 2013: 194-203 - 2012
- [c39]Susmita Sur-Kolay:
Intellectual property protection and security of SoCs - An embedded tutorial. SoCC 2012: 289 - [c38]Sudhindu Bikash Mandal
A Synthesis Method for Quaternary Quantum Logic Circuits. VDAT 2012: 270-280 - [c37]Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal:
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT 2012: 327-336 - [c36]Susmita Sur-Kolay, Swarup Bhunia:
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. VLSI Design 2012: 18-19 - 2011
- [c35]Sudhindu Bikash Mandal
Synthesis Techniques for Ternary Quantum Logic. ISMVL 2011: 218-223 - [c34]Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay:
TSV-aware Scan Chain Reordering for 3D IC. ISVLSI 2011: 188-193 - 2010
- [c33]Debasri Saha, Susmita Sur-Kolay:
A Unified Approach for IP Protection across Design Phases in a Packaged Chip. VLSI Design 2010: 105-110 - 2009
- [c32]Debasri Saha, Susmita Sur-Kolay:
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design. ISVLSI 2009: 169-174 - [c31]Pritha Banerjee
Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design 2009: 125-130 - [c30]Debasri Saha, Susmita Sur-Kolay:
Encoding of Floorplans through Deterministic Perturbation. VLSI Design 2009: 315-320 - 2008
- [c29]Debasri Saha, Susmita Sur-Kolay:
An Analytical Approach to Direct IP Protection of VLSI Floorplans. ICIIS 2008: 1-6 - 2007
- [c28]Debasri Saha, Susmita Sur-Kolay:
Fast Robust Intellectual Property Protection for VLSI Physical Design. ICIT 2007: 1-6 - [c27]Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma:
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA 2007: 111-116 - [c26]Pritha Banerjee
Faster Placer for Island-Style FPGAs. ICCTA 2007: 117-121 - [c25]Pritha Banerjee
Floorplanning in Modern FPGAs. VLSI Design 2007: 893-898 - 2006
- [c24]Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta:
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT 2006: 281-284 - [c23]Debasis Mitra, Subhasis Bhattacharjee
Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348 - 2005
- [c22]Pritha Banerjee
Fast FPGA Placement using Space-filling Curve. FPL 2005: 415-420 - [c21]Susmita Sur-Kolay, Satyajit Banerjee, Srabani Mukhopadhyaya
Genetic Algorithm for Double Digest Problem. PReMI 2005: 623-629 - [c20]Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty:
Hot Spots and Zones in a Chip: A Geometrician's View. VLSI Design 2005: 691-696 - 2004
- [c19]Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083 - [c18]Sanjay Goswami, Susmita Sur-Kolay:
Virtual Molecular Computing - Emulating DNA Molecules. IWDC 2004: 95-101 - [c17]Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah:
Physical Design Trends and Layout-Based Fault Modeling. VLSI Design 2004: 6-8 - 2003
- [c16]Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy:
Flavours of Traveling Salesman Problem in VLSI Design. IICAI 2003: 656-667 - 2001
- [c15]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combining Instruction and Loop Level Parallelism for FPGAs. FCCM 2001: 273-282 - [c14]Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy:
Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. ISCAS (5) 2001: 395-398 - [c13]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170 - [c12]Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta:
Partitioning Routing Area into Zones with Distinct Pins. VLSI Design 2001: 345- - 2000
- [c11]Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy:
Fsimac: a fault simulator for asynchronous sequential circuits. Asian Test Symposium 2000: 114-119 - [c10]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159 - [c9]Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Topological Routing Amidst Polygonal Obstacles. VLSI Design 2000: 274-279 - 1998
- [c8]Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. VLSI Design 1998: 65- - 1997
- [c7]Parthasarathi Dasgupta, Susmita Sur-Kolay:
Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155 - 1995
- [c6]Abhik Roychoudhury
Efficient Algorithms for Vertex Arboricity of Planar Graphs. FSTTCS 1995: 37-51 - [c5]Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715 - [c4]P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
VLSI floorplan generation and area optimization using AND-OR graph search. VLSI Design 1995: 370-375 - 1992
- [c3]Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. DAC 1992: 69-74 - 1991
- [c2]Susmita Sur-Kolay, Bhargab B. Bhattacharya:
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. ICCD 1991: 524-527 - 1988
- [c1]Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. FSTTCS 1988: 88-107
Reference Works
- 2008
- [r1]Susmita Sur-Kolay:
Floorplanning. Handbook of Algorithms for Physical Design Automation 2008
Informal and Other Publications
- 2024
- [i20]Rikathi Pal, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay:
Panoptic Segmentation and Labelling of Lumbar Spine Vertebrae using Modified Attention Unet. CoRR abs/2404.18291 (2024) - [i19]Rikathi Pal, Sudeshna Mondal, Aditi Gupta, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay:
Lumbar Spine Tumor Segmentation and Localization in T2 MRI Images Using AI. CoRR abs/2405.04023 (2024) - [i18]Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay:
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs. CoRR abs/2405.19948 (2024) - [i17]Debasmita Bhoumik, Ritajit Majumdar, Susmita Sur-Kolay:
Resource-aware scheduling of multiple quantum circuits on a hardware device. CoRR abs/2407.08930 (2024) - 2023
- [i16]Somoballi Ghoshal, Shremoyee Goswami, Amlan Chakrabarti, Susmita Sur-Kolay:
Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing. CoRR abs/2303.09523 (2023) - [i15]Mukta Debnath, Krishnendu Guha, Debasri Saha, Susmita Sur-Kolay:
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud. CoRR abs/2309.16282 (2023) - [i14]Saikat Basu, Arnav Das
FragQC: An Efficient Quantum Error Reduction Technique using Quantum Circuit Fragmentation. CoRR abs/2310.00444 (2023) - 2022
- [i13]Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay:
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution. CoRR abs/2205.04047 (2022) - [i12]Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay:
Efficient Machine-Learning-based decoder for Heavy Hexagonal QECC. CoRR abs/2210.09730 (2022) - 2021
- [i11]Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay:
Optimizing Ansatz Design in QAOA for Max-cut. CoRR abs/2106.02812 (2021) - [i10]Ritajit Majumdar, Debasmita Bhoumik, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay:
Depth Optimized Ansatz Circuit in QAOA for Max-Cut. CoRR abs/2110.04637 (2021) - [i9]Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay:
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs. CoRR abs/2111.00805 (2021) - 2020
- [i8]Ritajit Majumdar, Susmita Sur-Kolay:
Exploiting degeneracy to construct good ternary quantum error correcting code. CoRR abs/2008.00713 (2020) - [i7]Amit Saha, Ritajit Majumdar, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay:
Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate. CoRR abs/2012.04447 (2020) - 2018
- [i6]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR abs/1810.10412 (2018) - [i5]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR abs/1810.12789 (2018) - [i4]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR abs/1811.05161 (2018) - 2016
- [i3]Ritajit Majumdar, Saikat Basu
Error tracing in linear and concatenated quantum circuits. CoRR abs/1612.08044 (2016) - 2012
- [i2]Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay:
A Synthesis Method for Quaternary Quantum Logic Circuits. CoRR abs/1210.8055 (2012) - 2011
- [i1]Amlan Chakrabarti, Susmita Sur-Kolay, Ayan Chaudhury:
Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning. CoRR abs/1112.0564 (2011)
Coauthor Index
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last updated on 2024-10-07 21:15 CEST by the dblp team
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