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Anuja Sehgal
Person information
- affiliation: NVidia
- affiliation (former): AMD
- affiliation (former): Duke University, Durham, NC, USA
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2000 – 2009
- 2009
- [j6]Ozgur Sinanoglu
, Erik Jan Marinissen
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. 26(3): 25-37 (2009) - [j5]Sandeep Kumar Goel, Erik Jan Marinissen
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009) - [c12]Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test access mechanism for multiple identical cores. ITC 2009: 1-10 - 2008
- [j4]Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13(3): 53:1-53:19 (2008) - [c11]Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test Access Mechanism for Multiple Identical Cores. ITC 2008: 1-10 - 2007
- [j3]Anuja Sehgal, Krishnendu Chakrabarty:
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Trans. Computers 56(1): 120-133 (2007) - [c10]Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick:
Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC 2007: 1-10 - [i1]Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty:
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. CoRR abs/0710.4686 (2007) - 2006
- [j2]Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty:
Test infrastructure design for mixed-signal SOCs with wrapped analog cores. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 292-304 (2006) - [c9]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290 - 2005
- [c8]Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. DATE 2005: 50-55 - [c7]Anuja Sehgal, Krishnendu Chakrabarty
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. ICCAD 2005: 88-93 - [c6]Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. ICCD 2005: 137-142 - 2004
- [j1]Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
SOC test planning using virtual test access architectures. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1263-1276 (2004) - [c5]Anuja Sehgal, Krishnendu Chakrabarty
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. DATE 2004: 422-427 - [c4]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212 - 2003
- [c3]Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty:
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. DAC 2003: 738-743 - [c2]Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen
Yield analysis for repairable embedded memories. ETW 2003: 35-40 - [c1]Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty:
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. ICCAD 2003: 95-99
Coauthor Index
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