Article

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers

Authors:

Vikram Iyengar,

Mark D. Krasniewski,

Krishnendu ChakrabartyAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 738 - 743

https://doi.org/10.1145/775832.776021

Published: 02 June 2003 Publication History

Abstract

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high speed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks.

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Cited By

Rau JWu PMa J(2018)An efficient scheduling algorithm based on multi-frequency tam for SOC testingWSEAS Transactions on Circuits and Systems10.5555/1482107.14821197:6(558-568)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.5555/1482107.1482119
Giri CTipparthi DChattopadhyay S(2018)A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraintWSEAS Transactions on Circuits and Systems10.5555/1482066.14820777:5(416-427)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.5555/1482066.1482077
Rau JWu PChien CWu C(2018)The efficient TAM design for core-based SOCs testingWSEAS Transactions on Circuits and Systems10.5555/1482011.14820127:11(922-931)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.5555/1482011.1482012
Show More Cited By

Index Terms

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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Information

Published In

cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Rau JWu PMa J(2018)An efficient scheduling algorithm based on multi-frequency tam for SOC testingWSEAS Transactions on Circuits and Systems10.5555/1482107.14821197:6(558-568)Online publication date: 21-Dec-2018
Giri CTipparthi DChattopadhyay S(2018)A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraintWSEAS Transactions on Circuits and Systems10.5555/1482066.14820777:5(416-427)Online publication date: 21-Dec-2018
Rau JWu PChien CWu C(2018)The efficient TAM design for core-based SOCs testingWSEAS Transactions on Circuits and Systems10.5555/1482011.14820127:11(922-931)Online publication date: 21-Dec-2018
Hussin FYoneda TOrailoĞLu AFujiwara H(2018)Scheduling Power-Constrained Tests through the SoC Functional BusIEICE - Transactions on Information and Systems10.1093/ietisy/e91-d.3.736E91-D:3(736-746)Online publication date: 16-Dec-2018
Ghosh SSrivastava R(2013)CPK Based IO AC Timing Closure to Reduce Yield Loss and Test TimeVLSI Design and Test10.1007/978-3-642-42024-5_31(257-266)Online publication date: 2013
Zhao DHuang RFujiwara H(2007)Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.79(107-110)Online publication date: Oct-2007
Zhao DChandran UFujiwara H(2007)Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358071(714-719)Online publication date: Jan-2007
Wang (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
Yoneda TMasuda KFujiwara HGielen G(2006)Power-constrained test scheduling for multi-clock domain SoCsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131563(297-302)Online publication date: 6-Mar-2006
Liu C(2006)Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking2006 15th Asian Test Symposium10.1109/ATS.2006.260966(431-436)Online publication date: Dec-2006
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