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"Hierarchy-aware and area-efficient test infrastructure design for ..."

Anuja Sehgal et al. (2006)

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DOI: 10.1109/DATE.2006.244140

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - conf/date/SehgalGMC06
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  - https://dblp.org/rec/conf/date/SehgalGMC06
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290

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