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Jeff Rearick
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2020 – today
- 2023
- [c40]Li-C. Wang, Jeff Rearick:
Welcome Message ITC 2023. ITC 2023: xiii - [c39]Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg:
Refreshing the JTAG Family. VTS 2023: 1-7 - 2022
- [c38]Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo:
IEEE P1687.1: Extending the Network Boundaries for Test. ITC 2022: 382-390 - 2021
- [c37]Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim:
Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS 2021: 1-10 - 2020
- [c36]Michele Portolan, Jeff Rearick, Martin Keim:
Linking Chip, Board, and System Test via Standards. ETS 2020: 1-8 - [c35]Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick:
Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC 2020: 1-10 - [c34]Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne:
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices. ITC 2020: 1-10
2010 – 2019
- 2019
- [c33]Jeff Rearick, Alfred L. Crouch, Hans Martin von Staudt:
Innovative Practices on IEEE 1687.xyz. VTS 2019: 1 - 2018
- [c32]Wim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick:
Innovative practices on quality levels of A/MS devices. VTS 2018: 1 - 2017
- [j5]Michael Alfano, Bryan Black, Jeff Rearick, Joseph Siegel, Michael Su, Julius Din:
Unleashing Fury: A New Paradigm for 3-D Design and Test. IEEE Des. Test 34(1): 8-15 (2017) - [c31]Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood:
Maximizing scan pin and bandwidth utilization with a scan routing fabric. ITC 2017: 1-10 - [c30]Peter Sarson, Jeff Rearick:
Use models for extending IEEE 1687 to analog test. ITC 2017: 1-8 - 2016
- [j4]Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick:
Streaming Access to ADCs and DACs for Mixed-Signal ATPG. IEEE Des. Test 33(6): 38-45 (2016) - [c29]Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood:
Toward more efficient scan data bandwidth utilization on modern SOCs. SoCC 2016: 64-68 - 2015
- [c28]Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick:
Streaming fast access to ADCs and DACs for mixed-signal ATPG. ITC 2015: 1-8 - 2014
- [c27]Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick:
Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns. ITC 2014: 1-8 - 2013
- [c26]Jeff Rearick:
Magical thinking applied to test engineering reality (and vice versa). ETS 2013: 1 - 2012
- [c25]Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman
, Krishnendu Chakrabarty
Re-using chip level DFT at board level. ETS 2012: 1 - 2011
- [c24]Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick:
Structural tests of slave clock gating in low-power flip-flop. VTS 2011: 254-259 - 2010
- [c23]Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday:
Vendor-agnostic native compression engine. ITC 2010: 819 - [c22]Janine Chen, Jing Zeng, Li-C. Wang
Selecting the most relevant structural Fmax for system Fmax correlation. VTS 2010: 99-104
2000 – 2009
- 2009
- [j3]Ozgur Sinanoglu
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. 26(3): 25-37 (2009) - [c21]Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick:
Cache-resident self-testing for I/O circuitry. ITC 2009: 1-8 - [c20]Ken Posse, Al Crouch, Jeff Rearick:
IEEE P1687 IJTAG a presentation of current technology. ITC 2009: 1 - 2008
- [j2]Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick:
Overview of Debug Standardization Activities. IEEE Des. Test Comput. 25(3): 258-267 (2008) - [c19]Jeff Rearick:
This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. ITC 2008 - 2007
- [j1]Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick:
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. IEEE Des. Test Comput. 24(4): 362-372 (2007) - [c18]Jeff Rearick:
Embedded Test Features for High-Speed Serial I/O. CICC 2007: 153-156 - [c17]Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick:
Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC 2007: 1-10 - 2006
- [c16]Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote:
IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC 2006: 1-8 - [c15]Jeff Rearick:
A Survey of Test Problems and Solutions. ITC 2006: 1-10 - [c14]Jeff Rearick, Aaron Volz:
A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. ITC 2006: 1-8 - 2005
- [c13]Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts:
IJTAG (internal JTAG): a step toward a DFT standard. ITC 2005: 8 - [c12]Jeff Rearick, Richard Rodgers:
Calibrating clock stretch during AC scan testing. ITC 2005: 8 - 2004
- [c11]Jeff Rearick, Sylvia Patterson, Krista Dorner:
Integrating Boundary Scan into Multi-GHz I/O Circuitry. ITC 2004: 560-566 - 2003
- [c10]Suzette Vandivier, Mark Wahl, Jeff Rearick:
First IC Validation of IEEE Std. 1149.6. ITC 2003: 632-639 - [c9]Manish Sharma, Janak H. Patel, Jeff Rearick:
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS 2003: 15-21 - 2001
- [c8]Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick:
Frequency detection-based boundary-scan testing of AC coupled nets. ITC 2001: 46-53 - [c7]Jeff Rearick:
Too much delay fault coverage is a bad thing. ITC 2001: 624-633 - 2000
- [c6]Peter C. Maxwell, Jeff Rearick:
Deception by design: fooling ourselves with gate-level models. ITC 2000: 921-929
1990 – 1999
- 1999
- [c5]Jeff Rearick:
Practical scan test generation and application for embedded FIFOs. ITC 1999: 294-300 - 1998
- [c4]Peter C. Maxwell, Jeff Rearick:
Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ITC 1998: 882-889 - [c3]Jeff Rearick:
Buying time for the stuck-at fault model. ITC 1998: 1167 - 1997
- [c2]Jeff Rearick:
The Case of Partial Scan. ITC 1997: 1032 - 1993
- [c1]Jeff Rearick, Janak H. Patel:
Fast and Accurate CMOS Bridging Fault Simulation. ITC 1993: 54-62
Coauthor Index
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