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29th ETS 2024: The Hague, Netherlands
- IEEE European Test Symposium, ETS 2024, The Hague, Netherlands, May 20-24, 2024. IEEE 2024, ISBN 979-8-3503-4932-0
- Tolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev:
Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling. 1-6 - Denis Schwachhofer
, Francesco Angione
Optimizing System-Level Test Program Generation via Genetic Programming. 1-4 - Yu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin:
GNN-Based INC and IVC Co-Optimization for Aging Mitigation. 1-4 - Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin:
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. 1-4 - Mohamed A. Nadeem
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. 1-6 - Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. 1-6 - Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Resilience Metric Characterization in Complex Digital Systems. 1-4 - Pei-Yun Lin, Jin-Fu Li:
Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs. 1-4 - Gaurav Singh
On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing. 1-6 - Juergen Alt:
It is All About Trust: The Road to Autonomous Driving Will Connect Test, Reliability and Safety. 1 - Davide Turossi
A SystemC-AMS Development Framework for High Power IC Test-Hardware. 1-5 - Ric Dokken:
Hardware-Independent ATE Software for SLT. 1-4 - Shlomo Engelberg, Osnat Keren:
Hardening Bus-Encoders with Power-Aware Single Error Correcting Codes. 1-4 - Han Yan, Shuai Chen, Junying Huang, Jing Ye, Huawei Li, Xiaowei Li:
A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. 1-4 - Dimitris Gizopoulos, George Papadimitriou, Odysseas Chatzopoulos, Nikos Karystinos, Harish Dattatraya Dixit, Sriram Sankar:
Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements. 1-10 - Michele Portolan, Martin Keim, J. F. Coté, Hans-Martin Von Staud:
What Would Interactive Testing With 1687 Look Like? 1 - Aniruddha Datta, Bhanu Vikas Yaganti, Andrew Dove, Arik Peltz, Krishnendu Chakrabarty:
Test-Fleet Optimization Using Machine Learning. 1-10 - Jongsin Yun, Sina Bakhtavari Mamaghani, Mehdi B. Tahoori, Christopher Münch, Martin Keim:
MBIST-based weak bit screening method for embedded MRAM. 1-4 - Troya Çagil Köylü, Cornelis Christiaan Berg, Praveen Kumar Vadnala:
CGAN-based Automated Fault Injection. 1-6 - Dennis Gnad, Martin Gotthard, Jonas Krautter, Angeliki Kritikakou, Vincent Meyers, Paolo Rech, Josie E. Rodriguez Condia, Annachiara Ruospo, Ernesto Sánchez, Fernando Fernandes dos Santos, Olivier Sentieys, Mehdi B. Tahoori, Russell Tessier, Marcello Traiola:
Reliability and Security of AI Hardware. 1-10 - Rama Govindaraju:
Silent Data Corruption Errors in VLSI Circuits: Implications, Challenges, and Opportunities. 1 - Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera
Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations. 1-4 - Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli
Test and Repair Improvements for UCIe. 1-6 - Seyedeh Maryam Ghasemi, Jonas Krautter, Tara Gheshlaghi, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori:
Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V. 1-6 - Pushpak Raj Gautam, Alex Orailoglu:
Transcoders: A Better Alternative To Denoising Autoencoders. 1-4 - Hanzhi Xun, Moritz Fieback
Online Detection of Unique Faults in RRAMs. 1-2 - Cheng-Wen Wu, Shi-Yu Huang:
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. 1-2 - Yong Liu, Yuejun Liu, Yongbin Zhou, Yiwen Gao, Zehua Qiao, Huaxin Wang:
A Novel Power Analysis Attack against CRYSTALS-Dilithium Implementation. 1-6 - Denis Schwachhofer
Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties. 1-4 - Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim:
Combining Built-In Redundancy Analysis with ECC for Memory Testing. 1-6 - Chris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. Shawn Blanton:
Faulty Function Extraction for Defective Circuits. 1-6 - Nassim Riadi
Power Analysis Attack Against post-SAT Logic Locking schemes. 1-6 - Priyanjana Pal, Florentia Afentaki, Haibin Zhao
Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers. 1-6 - Xin-Ping Chen, Hsu-Yu Huang, Chu-Yun Hsiao, Jennifer Shueh-Inn Hu, James Chien-Mo Li:
Test Compression for Neuromorphic Chips. 1-6 - Suhasini Komarraju, Mohamed Mejri, Akhil Tammana, Gowsika Dharmaraj, Chandramouli N. Amarnath, Abhijit Chatterjee:
AMS Test Stimulus Generation and Response Analysis Using Hyperdimensional Clustering: Minimizing Misclassification Rate. 1-4 - Fouwad Jamil Mir, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil:
Extracting Weights of CIM-Based Neural Networks Through Power Analysis of Adder-Trees. 1-4 - Moritz Fieback
Lifecycle Management of Emerging Memories. 1-6 - Riccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti, Reza Khoshzaban
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test. 1-4 - Juan Suzano, Antoine Chastand, Emanuele Valea, Giorgio Di Natale, Anthony Philippe, Fady Abouzeid, Philippe Roche:
IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs. 1-6 - Adit D. Singh:
Silent Data Corruption from Timing Marginalities Due to Process Variations. 1-7 - Sandeep Kumar Goel, Ankita Patidar, Frank Lee:
Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. 1-4 - Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen:
Silent Data Corruption: Test or Reliability Problem? 1-7 - Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra:
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. 1-10 - Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler:
A Multi-Objective Evolutionary Approach for Test Network Design. 1-4 - Anurup Saha, Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee:
Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery. 1-4 - David C. Keezer
Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz. 1-6 - Vladimir A. Zivkovic, Inga Abel, Anthony Candage:
A Concept of Provably Detected Defects for Analog Defect Simulation Campaign Improvement. 1-4 - Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini:
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. 1-6 - Christoph Hazott, Daniel Große:
Relation Coverage: A New Paradigm for Hardware/Software Testing. 1-4 - Sicong Yuan, Mohammad Amin Yaldagard
Design-for-Test for Intermittent Faults in STT-MRAMs. 1-6 - Stefan A. Lung, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil:
Counteracting Rowhammer by Data Alternation. 1-6 - Marcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anil Bayram Gogebakan, Enrico Magliano, Alessandro Savino
Approximate Fault-Tolerant Neural Network Systems. 1-10 - Heguo Yin, Peter Poechmueller:
Semiconductor Application Fail Root Causes And Secure Test Remedy. 1-6 - Jayeeta Chaudhuri, Krishnendu Chakrabarty:
Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks. 1-6 - Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. 1-4 - Aghiles Douadi, Elena-Ioana Vatajelu, Paolo Maistri, David Hély, Vincent Beroulle, Giorgio Di Natale:
Modeling Thermal Effects For Biasing PUFs. 1-4 - Soyed Tuhin Ahmed
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. 1-6
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last updated on 2024-11-22 19:32 CET by the dblp team
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