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Arnaud Tisserand
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2020 – today
- 2023
- [c45]Morgane Vollmer, Karim Bigou, Arnaud Tisserand:
Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context. ARITH 2023: 84-87 - [c44]Fabrice Lozachmeur, Arnaud Tisserand:
A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders. MWSCAS 2023: 360-364 - 2022
- [j22]Timo Zijlstra, Karim Bigou
, Arnaud Tisserand
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS. IEEE Trans. Computers 71(8): 1916-1927 (2022) - [c43]Noura Ait Manssour, Vianney Lapôtre, Guy Gogniat
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks. DDECS 2022: 26-31
2010 – 2019
- 2019
- [j21]Gabriel Gallin
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs. IEEE Trans. Computers 68(11): 1612-1622 (2019) - [c42]Libey Djath, Karim Bigou
Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography. ARITH 2019: 46-53 - [c41]Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand:
Evaluation of variable bit-width units in a RISC-V processor for approximate computing. CF 2019: 344-349 - [c40]Timo Zijlstra, Karim Bigou
FPGA Implementation and Comparison of Protections Against SCAs for RLWE. INDOCRYPT 2019: 535-555 - 2018
- [j20]Vincent Migliore
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm. IEEE Trans. Computers 67(3): 335-347 (2018) - [j19]Diego F. G. Coelho
Computation of 2D 8×8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding. IEEE Trans. Computers 67(12): 1692-1702 (2018) - [c39]Audrey Lucas, Arnaud Tisserand:
Microcontroller Implementation of Simultaneous Protections Against Observation and Perturbation Attacks for ECC. ICETE (2) 2018: 570-577 - [c38]Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand:
Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform. SAMOS 2018: 146-149 - 2017
- [j18]Javier Hormigo
Introduction to the Special Issue on Computer Arithmetic. IEEE Trans. Computers 66(12): 1991-1993 (2017) - [j17]Vincent Migliore, Cédric Seguin, Maria Mendez Real
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm. ACM Trans. Embed. Comput. Syst. 16(5s): 138:1-138:17 (2017) - [c37]Gabriel Gallin, Arnaud Tisserand:
Hyper-threaded multiplier for HECC. ACSSC 2017: 447-451 - [c36]Imran Wali, Emmanuel Casseau, Arnaud Tisserand:
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. DASIP 2017: 1-6 - [c35]Gabriel Gallin, Türkü Özlüm Çelik, Arnaud Tisserand
Architecture Level Optimizations for Kummer Based HECC on FPGAs. INDOCRYPT 2017: 44-64 - [i2]Gabriel Gallin, Türkü Özlüm Çelik, Arnaud Tisserand:
Architecture level Optimizations for Kummer based HECC on FPGAs. IACR Cryptol. ePrint Arch. 2017: 1009 (2017) - 2016
- [j16]Karim Bigou
Binary-Ternary Plus-Minus Modular Inversion in RNS. IEEE Trans. Computers 65(11): 3495-3501 (2016) - [c34]Karim Bigou
Hybrid Position-Residues Number System. ARITH 2016: 126-133 - [c33]Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm. FPT 2016: 209-212 - 2015
- [j15]Ghada Y. Abozaid
Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier. IEEE Embed. Syst. Lett. 7(3): 77-80 (2015) - [c32]Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. ASYNC 2015: 132-138 - [c31]Karim Bigou
Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC. CHES 2015: 123-140 - [c30]Danuta Pamula, Arnaud Tisserand:
Fast and Secure Finite Field Multipliers. DSD 2015: 653-660 - [c29]Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau:
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). ISVLSI 2015: 440-445 - [c28]Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat
Exploration of polynomial multiplication algorithms for homomorphic encryption schemes. ReConFig 2015: 1-6 - [i1]Karim Bigou, Arnaud Tisserand:
Improving Modular Inversion in RNS using the Plus-Minus Method. IACR Cryptol. ePrint Arch. 2015: 193 (2015) - 2014
- [c27]Karim Bigou
RNS modular multiplication through reduced base extensions. ASAP 2014: 57-62 - [c26]Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
Robust sub-powered asynchronous logic. PATMOS 2014: 1-7 - 2013
- [j14]Loïc Lagadec, Sébastien Pillement, Arnaud Tisserand:
Introduction. Tech. Sci. Informatiques 32(2): 149-151 (2013) - [c25]Thomas Chabrier, Arnaud Tisserand:
On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations. IEEE Symposium on Computer Arithmetic 2013: 219-228 - [c24]Karim Bigou
Improving Modular Inversion in RNS Using the Plus-Minus Method. CHES 2013: 233-249 - 2012
- [c23]Danuta Pamula, Edward Hrynkiewicz, Arnaud Tisserand:
Analysis of GF (2233) multipliers regarding elliptic curve cryptosystem applications. PDeS 2012: 271-276 - [c22]Danuta Pamula, Arnaud Tisserand:
$\textrm{GF}(2^m)$ Finite-Field Multipliers with Reduced Activity Variations. WAIFI 2012: 152-167 - 2011
- [c21]Mark Hamilton, William P. Marnane
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values. FPL 2011: 273-276 - 2010
- [b2]Arnaud Tisserand:
Étude et conception d'opérateurs arithmétiques. (Study and design of arithmetic operators). University of Rennes 1, France, 2010 - [c20]Danuta Pamula, Edward Hrynkiewicz, Arnaud Tisserand:
Multiplication in GF(2m): Area and time dependency/efficiency/complexity analysis. PDeS 2010: 28-33
2000 – 2009
- 2009
- [c19]Caroline Collange, David Defour, Arnaud Tisserand:
Power Consumption of GPUs from a Software Perspective. ICCS (1) 2009: 914-923 - [c18]Pascal Giorgi, Thomas Izard, Arnaud Tisserand:
Comparison of Modular Arithmetic Algorithms on GPUs. PARCO 2009: 315-322 - 2008
- [j13]Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Optimisation d'opérateurs arithmétiques matériels à base d'approximations polynomiales. Tech. Sci. Informatiques 27(6): 699-718 (2008) - [c17]Arnaud Tisserand:
Fast and accurate activity evaluation in multipliers. ACSCC 2008: 757-761 - [c16]Julien Francq, Jean-Baptiste Rigaud
Error Detection for Borrow-Save Adders Dedicated to ECC Unit. FDTC 2008: 77-86 - 2007
- [j12]Arnaud Tisserand:
High-performance hardware operators for polynomial evaluation. Int. J. High Perform. Syst. Archit. 1(1): 14-23 (2007) - [j11]Andrew Byrne, Francis M. Crowe, William P. Marnane, Nicolas Méloni, Arnaud Tisserand, Emanuel M. Popovici:
SPA resistant elliptic curve cryptosystem using addition chains. Int. J. High Perform. Syst. Archit. 1(2): 133-142 (2007) - [j10]Andrew Byrne, Nicolas Méloni, Arnaud Tisserand, Emanuel M. Popovici, William P. Marnane:
Comparison of Simple Power Analysis Attack Resistant Algorithms for an Elliptic Curve Cryptosystem. J. Comput. 2(10): 52-62 (2007) - [j9]Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Multi-mode operator for SHA-2 hash functions. J. Syst. Archit. 53(2-3): 127-138 (2007) - [j8]Arnaud Tisserand:
Chronique : Introduction aux représentations des nombres et opérateurs arithmétiques à basse consommation d'énergie. Tech. Sci. Informatiques 26(5): 639-646 (2007) - [c15]Andrew Byrne, Nicolas Méloni, Francis M. Crowe, William P. Marnane
SPA resistant Elliptic Curve Cryptosystem using Addition Chains. ITNG 2007: 995-1000 - 2006
- [j7]Nicolas Brisebarre, Jean-Michel Muller
Computing machine-efficient polynomial approximations. ACM Trans. Math. Softw. 32(2): 236-256 (2006) - [c14]Rachid Beguenane, Jean-Gabriel Mailloux, Stéphane Simard, Arnaud Tisserand:
Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time. CCECE 2006: 1073-1077 - [c13]Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Multi-Mode Operator for SHA-2 Hash Functions. ERSA 2006: 207-210 - [c12]Arnaud Tisserand:
Hardware Operator for Simultaneous Sine and Cosine Evaluation. ICASSP (3) 2006: 992-995 - [c11]Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Carry Prediction and Selection for Truncated Multiplication. SiPS 2006: 339-344 - 2005
- [j6]Florent de Dinechin, Arnaud Tisserand:
Multipartite Table Methods. IEEE Trans. Computers 54(3): 319-330 (2005) - [j5]Nicolas Boullis, Arnaud Tisserand:
Some Optimizations of Hardware Multiplication by Constant Matrices. IEEE Trans. Computers 54(10): 1271-1282 (2005) - [c10]Jean-Michel Muller
Division by Constant for the ST100 DSP Microprocessor. IEEE Symposium on Computer Arithmetic 2005: 124-130 - [c9]Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x. ASAP 2005: 334-342 - 2004
- [j4]Jean-Luc Beuchat
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA. Tech. Sci. Informatiques 23(10): 1247-1267 (2004) - 2003
- [c8]Nicolas Boullis, Arnaud Tisserand:
Some Optimizations of Hardware Multiplication by Constant Matrices. IEEE Symposium on Computer Arithmetic 2003: 20-27 - 2002
- [c7]Jean-Luc Beuchat
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. FPL 2002: 513-522 - 2001
- [c6]Florent de Dinechin, Arnaud Tisserand:
Some Improvements on Multipartite Table Methods . IEEE Symposium on Computer Arithmetic 2001: 128-135 - 2000
- [j3]Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. IEEE Trans. Computers 49(7): 628-637 (2000)
1990 – 1999
- 1999
- [c5]Arnaud Tisserand, Pierre Marchal, Christian Piguet:
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing. FPL 1999: 264-273 - 1998
- [j2]Jean-Michel Muller
Semi-Logarithmic Number Systems. IEEE Trans. Computers 47(2): 145-151 (1998) - [j1]Vincent Lefèvre, Jean-Michel Muller
Toward Correctly Rounded Transcendentals. IEEE Trans. Computers 47(11): 1235-1243 (1998) - [c4]Pascal Nussbaum, Bernard Girau, Arnaud Tisserand:
Field Programmable Processor Arrays. ICES 1998: 311-322 - 1997
- [b1]Arnaud Tisserand:
Adéquation arithmétique architecture, problèmes et étude de cas. (Arithmetic architecture adequacy, problems and case study). École normale supérieure de Lyon, France, 1997 - [c3]Vincent Lefèvre, Arnaud Tisserand, Jean-Michel Muller
Towards Correctly Rounded Transcendentals. IEEE Symposium on Computer Arithmetic 1997: 132- - [c2]Arnaud Tisserand, Martin Dimmler:
FPGA implementation of real-time digital controllers using on-line arithmetic. FPL 1997: 472-481 - 1995
- [c1]Jean-Michel Muller
Semi-Logarithmic Number Systems. IEEE Symposium on Computer Arithmetic 1995: 201-207
Coauthor Index
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