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Tiago T. Jost
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2020 – today
- 2023
- [c11]Arun Thangamani, Tiago Trevisan Jost, Vincent Loechner, Stéphane Genaud, Bérenger Bramas:
Lifting Code Generation of Cardiac Physiology Simulation to Novel Compiler Technology. CGO 2023: 68-80 - [c10]Tiago Trevisan Jost
, Arun Thangamani
GPU Code Generation of Cardiac Electrophysiology Simulation with MLIR. Euro-Par 2023: 549-563 - 2021
- [b1]Tiago Trevisan Jost:
Compilation and optimizations for variable precision floating-Point arithmetic : from language and libraries to code generation. (Compilation et optimisations pour l'arithmétique à virgule flottante en précision variable : du langage et des bibliothèques à la génération de code). Grenoble Alpes University, France, 2021 - [c9]Tiago Trevisan Jost, Yves Durand, Christian Fabre
Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic. CGO 2021: 65-76 - 2020
- [j1]Tiago Trevisan Jost, Gabriel Luca Nazar, Luigi Carro:
SoMMA: A software-managed memory architecture for multi-issue processors. Microprocess. Microsystems 77: 103139 (2020) - [c8]Tiago T. Jost, Yves Durand, Christian Fabre
VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic. PACT 2020: 355-356
2010 – 2019
- 2019
- [c7]Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand:
Evaluation of variable bit-width units in a RISC-V processor for approximate computing. CF 2019: 344-349 - [c6]Andrea Bocco, Tiago T. Jost, Albert Cohen, Florent de Dinechin, Yves Durand, Christian Fabre
Byte-Aware Floating-point Operations through a UNUM Computing Unit. VLSI-SoC 2019: 323-328 - 2018
- [c5]Pedro Henrique Exenberger Becker
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. ARC 2018: 499-510 - [c4]Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand:
Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform. SAMOS 2018: 146-149 - 2017
- [c3]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
An energy-efficient memory hierarchy for multi-issue processors. DATE 2017: 368-373 - 2016
- [c2]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Scalable memory architecture for soft-core processors. ICCD 2016: 396-399 - [c1]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Improving performance in VLIW soft-core processors through software-controlled scratchpads. SAMOS 2016: 172-179
Coauthor Index
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